Image Data Clock-Domain Buffering for Variable Frame Rate Displays
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Solution Overview
Problem
The disconnection of signal transmission between intermediate devices and display terminals occurs due to the inability of interfaces to dynamically adjust the reference clock when the frame rate of a video signal changes, leading to abnormal display on the terminal.
Innovation Solution
An image data transmission device that includes a receiving sub-circuit, writing control component, reading control component, and sending component, which utilize separate clock domains and phase-locked loops to maintain stable signal transmission by adjusting to locked and unlocked states based on frame synchronous signals, ensuring continuous data transmission to the display.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the reference clock dynamically changes with frame rate, then the video signal can adapt to different frame rates, but the interface cannot support dynamic clock change causing signal disconnection
Solution Approach 1:
The patent implements dynamic clock domain separation where the receiving sub-circuit operates with a first clock domain that can dynamically adjust to different frame rates, while the sending sub-circuit operates with a second clock domain that maintains stable operation. The writing control component and reading control component dynamically switch between locked and unlocked states based on clock synchronization status, enabling the system to adapt to frame rate changes without causing signal disconnection.
Solution Approach 2:
The patent divides the image data transmission device into separate receiving and sending sub-circuits with independent clock domains. The receiving sub-circuit handles incoming video signals with variable frame rates using a first clock domain, while the sending sub-circuit outputs to the display terminal using a second clock domain. This segmentation allows each sub-circuit to independently manage clock synchronization, preventing signal disconnection when frame rates change.
2Reliability
If the interface uses a fixed clock domain, then signal transmission is stable, but it cannot adapt when the frame rate of the video signal changes
Solution Approach 1:
The patent implements dynamic clock domain separation where the receiving sub-circuit operates with a first clock domain that can dynamically adjust to different frame rates, while the sending sub-circuit operates with a second clock domain that maintains stable operation. The writing control component and reading control component dynamically switch between locked and unlocked states based on clock synchronization status, enabling the system to adapt to frame rate changes without causing signal disconnection.
3Adaptability or versatility
If the receiving sub-circuit locks to the incoming clock, then it can synchronize with the mainboard, but the sending sub-circuit cannot maintain stable output when the clock changes
Solution Approach 1:
The patent divides the image data transmission device into separate receiving and sending sub-circuits with independent clock domains. The receiving sub-circuit handles incoming video signals with variable frame rates using a first clock domain, while the sending sub-circuit outputs to the display terminal using a second clock domain. This segmentation allows each sub-circuit to independently manage clock synchronization, preventing signal disconnection when frame rates change.
Solution Approach 2:
The patent introduces a memory buffer as an intermediary between the receiving and sending sub-circuits. The writing control component writes received image data to the memory buffer according to the first frame synchronous signal, while the reading control component reads from the memory buffer according to the second frame synchronous signal. This intermediary buffer decouples the two clock domains, allowing the receiving sub-circuit to synchronize with the mainboard while the sending sub-circuit maintains stable output.
Data Source
AI summary
The disclosure provides an image data transmission device including: receiving sub-circuit, writing control component, and reading control component. The disclosure further provides an image data transmission method, including: in response to the receiving sub-circuit being in locked state, receiving, by receiving sub-circuit, image data sent by a mainboard, and writing, according to a first frame synchronous signal, the image data received from the mainboard in each clock cycle of the first frame synchronous signal into a frame of a memory, reading, according to a second frame synchronous signal, a frame from the memory in each clock cycle of the second frame synchronous signal; sending each frame read from the memory to a display component; and in response to the receiving sub-circuit being in unlocked state, stopping writing the image data into the memory. The disclosure further provides an electronic apparatus, a computer-readable medium and a display system.