Image Data Clock Control for Noise-Resilient Signal Processing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Data processing devices connected to external devices via transmission lines face issues with noise interference, particularly from static electricity, which can disrupt the clock signal and affect the processing of image data, leading to abnormal data output.
Innovation Solution
A data processing device with a data processing control circuit that operates with a lower impedance clock, allowing it to detect abnormalities in the external clock and discard affected data, thereby preventing noise-induced errors in data processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the data processing control circuit operates with the external clock signal, then the data processing can be synchronized with the external device, but the system becomes vulnerable to noise interference from the transmission line
Solution Approach 1:
The patent introduces an internal clock signal as an intermediary between the external clock and the data processing circuit. The internal clock is generated locally through a phase-locked loop (PLL) circuit that locks onto the external clock, thereby mediating the connection and isolating the data processing circuit from direct exposure to transmission line noise while maintaining synchronization.
Solution Approach 2:
The patent creates a copy of the external clock signal through the internal clock generation mechanism. Instead of using the noisy external clock directly, the system generates an internal copy that is cleaner and can be used for data processing without the harmful noise components, while still maintaining the same timing characteristics.
2Productivity
If the external clock signal is used directly for data processing, then synchronization with external devices is maintained, but abnormal data may be processed when noise affects the clock signal
Solution Approach 1:
The patent performs preliminary action by generating and stabilizing the internal clock signal before it is used for data processing. The phase-locked loop circuit预先 locks onto the external clock and produces a clean internal clock, ensuring that when data processing occurs, the clock signal is already prepared and free from noise-induced abnormalities.
Solution Approach 2:
The patent provides beforehand cushioning by creating a buffer zone between the noisy external clock and the data processing circuit through the internal clock generation mechanism. This cushioning protects the data processing from noise interference while maintaining synchronization, preventing abnormal data processing before it can occur.
3Ease of operation
If a higher impedance clock signal is used, then it is easier to couple with external devices, but it becomes more susceptible to noise from static electricity
Solution Approach 1:
The patent uses the internal clock signal as an intermediary that decouples the high-impedance external clock from the data processing circuit. The external device can still drive the high-impedance line easily, but the internal clock generated by the PLL provides a lower-impedance, noise-resistant signal for actual data processing.
Solution Approach 2:
The patent changes the impedance parameter of the clock signal through the internal generation mechanism. While the external interface maintains high impedance for ease of coupling, the internally generated clock signal has different electrical characteristics that are more resistant to static electricity noise, effectively changing the parameter where needed.
Data Source
AI summary
A data processing device includes a data processing circuit and a data processing control circuit. The data processing circuit is configured to perform data processing on processing target data by use of an external clock, the processing target data being included in a data signal received from an outside, the external clock being included in the data signal. The data processing control circuit is configured to detect a state of the external clock and control execution of the data processing on the processing target data in accordance with the state of the external clock. The data processing control circuit is configured to operate with a clock having a lower impedance than an impedance of the external clock, and discard the processing target data received during a period in which an abnormality of the external clock is detected, in a case of detecting the abnormality of the external clock.