Image Processing Core Allocation for Tile-Based Parallelism
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Solution Overview
Problem
Current image processing technologies using multiple cores face delays due to waiting times, which are not sufficiently reduced, especially with the increase in screen size and higher resolutions, leading to inefficiencies in video encoding and decoding processes.
Innovation Solution
An image processing apparatus is designed with multiple cores allocated to tiles of an image data, where cores are strategically allocated based on tile divisions in both directions, allowing for efficient parallel processing and reducing waiting times by optimizing core allocation and memory usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple cores are used for video encoding and decoding, then processing capacity is improved, but waiting times between cores occur causing delays
Solution Approach 1:
The image data is divided into multiple tiles, and each core is allocated to process specific tiles independently. This segmentation allows parallel processing without cores waiting for each other, as each core works on its assigned tiles autonomously
Solution Approach 2:
Tiles are divided in both horizontal and vertical directions, creating a two-dimensional tile grid. Cores are allocated to lines of tiles in either horizontal or vertical direction, adding a dimensional aspect to the parallel processing architecture that eliminates waiting times
2Manufacturing precision
If screen size increases to 4K and 8K resolutions, then image quality is improved, but processing time increases significantly
Solution Approach 1:
Large high-resolution images are divided into multiple smaller tiles, allowing parallel processing across multiple cores. This maintains image quality while reducing processing time by processing tiles simultaneously rather than sequentially
Solution Approach 2:
The patent creates an independent processing environment for each core by allocating specific tiles to each core, preventing processing bottlenecks and waiting times that would otherwise occur with sequential processing of large high-resolution images
3Productivity
If multiple cores are allocated to process tiles, then parallel processing is improved, but core waiting times occur due to processing order constraints
Solution Approach 1:
By organizing tiles into lines in either horizontal or vertical direction and allocating cores to these lines, the patent creates independent processing paths that eliminate waiting times. Each core processes its assigned line of tiles without depending on other cores
Solution Approach 2:
The system dynamically allocates cores to lines of tiles based on the tile grid configuration, allowing flexible parallel processing arrangements that adapt to different image sizes and resolutions while maintaining efficiency
Data Source
AI summary
An image processing apparatus includes a plurality of cores and an arithmetic processing device. The plurality of cores are configured to be allocated to a plurality of tiles obtained by dividing a single image data; a configured to control allocation of the plurality of cores based on the divided tiles. The arithmetic processing device is configured to control allocation of the plurality of cores based on the divided tiles. The arithmetic processing device allocates all of the plurality of cores to a single line of the plurality of tiles in a second direction, when the single image data is divided into the plurality of tiles in a first direction and the second direction different from the first direction.