Image Sensor Counter Shifting Circuit for Multi-Sample Area Reduction
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Solution Overview
Problem
Existing image sensors face challenges in minimizing the area occupied by counters while obtaining multiple samples, as the inclusion of increased circuits for storing all sampling results leads to space inefficiency.
Innovation Solution
The image sensor employs a counter that generates binary codes by comparing pixel signals with a ramp signal, utilizing a reset memory circuit to store the sum of N reset binary codes and perform a shifting operation to calculate a digital signal, reducing the need for individual latches by combining the storage of multiple reset signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a counter individually stores all sampling results, then multiple samples can be obtained, but the area occupied by the counter increases
Solution Approach 1:
The patent merges multiple individual storage locations into a single shared memory circuit. Instead of having separate latches for each sampling result, the invention uses one memory circuit to store multiple reset binary codes, thereby reducing the total counter area while maintaining the capability to obtain multiple samples.
Solution Approach 2:
The shared memory circuit performs multiple functions: it stores reset binary codes for different sampling operations, stores sum binary codes, and provides data for digital signal generation. This multi-functional approach eliminates the need for dedicated storage for each sampling result, reducing overall area.
2Measurement precision
If multiple latches are used to store sampling results, then all samples can be retained, but device complexity increases
Solution Approach 1:
Multiple latches are merged into a single shared memory circuit that handles all sampling results. This consolidation reduces the number of individual circuit components and simplifies the overall counter structure while preserving the ability to store and process multiple samples.
Solution Approach 2:
The patent introduces a sum binary code generation mechanism as an intermediary process. Instead of directly storing multiple individual samples, the system generates sum binary codes that represent aggregated sampling results, simplifying the storage and processing requirements.
3Reliability
If individual storage is used for each sampling result, then data integrity is maintained, but space efficiency decreases
Solution Approach 1:
The patent combines multiple individual storage units into a shared memory circuit that maintains data integrity through structured storage of reset binary codes and sum binary codes. The merging process preserves reliability by implementing organized data management within the shared resource.
Solution Approach 2:
The invention changes the storage parameter from individual separate latches to a shared memory structure with different storage modes (reset binary code storage and sum binary code storage). This parameter change enables more efficient space utilization while maintaining data integrity through structured data organization.
Data Source
AI summary
Disclosed is a counter which generates a binary code and a digital signal The counter includes: a reset memory circuit configured to store a sum of N reset binary codes, each of the N reset binary codes corresponding to a result of comparing a reset signal of the pixel signal with the ramp signal, and to calculate one of the N reset binary codes by performing a shifting operation on the sum of the N reset binary codes; and an output memory circuit configured to output the digital signal based on the N reset binary codes, a first image binary code indicating a result of comparing a first image signal of the pixel signal with the ramp signal once, and N sum binary codes, the N sum binary codes respectively indicating N results of comparing a sum signal of the pixel signal with the ramp signal.