Image Data Processing Using Line Memory Block Division

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Solution Overview

Problem

Conventional image processing technologies face challenges in noise reduction during high sensitivity photography, as low pass filters remove image edges, leading to decreased sharpness, and software-based noise removal methods are slow due to CPU limitations and discontinuous memory loading.

Innovation Solution

An apparatus and method that divide image data into blocks, store them in line memories, and generate data patches by sequentially accessing pixel values, allowing for efficient noise removal using a data patch generator and noise removal filter, which can be implemented using ASICs or FPGAs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If a low pass filter is used for noise reduction, then noise is removed, but image sharpness decreases due to removal of edge components

Engineering Contradiction:
ImprovenoiseVSAvoidimage sharpness
Core Design Contradiction:
Object-affected harmful factorsVSManufacturing precision

Solution Approach 1:

The image data is divided into multiple blocks, with each block processed independently to generate sub-sampled data. This segmentation allows selective processing of different regions, preserving edge information while removing noise in appropriate areas.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different processing approaches are applied to different regions of the image. Edge detection algorithms identify boundary regions where full-resolution data is preserved, while non-edge regions undergo sub-sampling for noise reduction, creating locally optimized quality throughout the image.

Inventive Principle:
Principle #3Local quality

2Manufacturing precision

If software-based noise removal is used, then noise can be removed while maintaining edges, but processing speed is slow due to CPU limitations and discontinuous memory loading

Engineering Contradiction:
Improveedge preservationVSAvoidprocessing speed
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The software-based CPU processing is replaced with a dedicated hardware apparatus consisting of line memories, block dividers, and data patch generators. This hardware implementation provides continuous, parallel processing capability that maintains edge preservation algorithms while dramatically increasing processing speed.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The line memories store image data in a continuous stream, allowing the hardware processor to continuously generate data patches without the discontinuous memory loading that occurs in software approaches. This continuous action eliminates CPU idle time and I/O wait states.

Inventive Principle:
Principle #20Continuity of useful action

3Ease of operation

If random access to storage device is used for sub-sampling, then image data can be read, but memory load becomes discontinuous causing apparatus overload and decreased processing speed

Engineering Contradiction:
Improvedata accessVSAvoidprocessing speed
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

Image data is pre-loaded into line memories in a continuous sequence before processing begins. This preliminary action ensures that all required data is readily available in fast memory, eliminating random access to slow storage devices during the actual processing phase and maintaining continuous operational flow.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8682024B2Apparatus for and method of processing image data
Publication Date: 2014.03.25 SAMSUNG ELECTRONICS CO LTD
  • US8682024B2 patent drawing
  • US8682024B2 patent drawing
  • US8682024B2 patent drawing

AI summary

An apparatus and method of processing image data sub-samples image data by generating a data patch by dividing the image data into a plurality of blocks and sequentially accessing pixel data values in each of the blocks through a plurality of line memories. The image data is divided into the plurality of blocks, the blocks are stored in each of the line memories, and the pixel data values stored in each of the line memories are sequentially accessed, so as to generate the data patch for sub-sampling the image data.