Image Decoding Device Divides Prediction Units to Reduce Memory Bandwidth
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Solution Overview
Problem
The H.265 video coding standard increases external memory bandwidth and processing time due to larger reference image sizes required for motion compensation, leading to performance issues in decoding and image output processing.
Innovation Solution
An image decoding device that divides prediction units into smaller blocks, regardless of transform unit size, to reduce processing time and memory bandwidth, allowing for efficient decoding without occupying external memory buses or increasing circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If motion compensation is performed using large prediction units in H.265 coding, then coding efficiency is improved, but external memory bandwidth and processing time increase
Solution Approach 1:
The prediction unit is divided into multiple sub-blocks for parallel processing. Each sub-block can be processed independently, allowing the system to handle large prediction units without requiring proportionally larger memory bandwidth, as the processing is distributed across multiple smaller units simultaneously.
Solution Approach 2:
The patent introduces a hierarchical processing structure where prediction units are organized in multiple layers (e.g., 64×64 PU divided into 16×16 sub-blocks). This dimensional organization allows efficient memory access patterns and parallel processing, reducing the actual memory bandwidth requirement while maintaining high coding efficiency.
2Measurement precision
If reference image size is increased for motion compensation, then prediction accuracy is improved, but processing time increases
Solution Approach 1:
The reference image processing is segmented into multiple independent sub-blocks that can be processed in parallel. This allows the system to work with large reference images for accurate motion compensation while reducing total processing time through concurrent execution of multiple smaller processing tasks.
Solution Approach 2:
The patent performs preliminary processing of reference images by organizing them into standardized block structures before actual motion compensation. This pre-organization allows faster access and processing during the actual decoding stage, reducing overall processing time while maintaining prediction accuracy.
3Ease of operation
If prediction units are processed as single large blocks, then decoding simplicity is maintained, but system performance deteriorates
Solution Approach 1:
The patent segments large prediction units into smaller sub-blocks that can be processed in parallel, improving system performance. The segmentation is designed to maintain regular block structures that preserve decoding simplicity, with clear hierarchical relationships between parent PUs and child sub-blocks.
Solution Approach 2:
The processing structure dynamically adapts to different prediction unit sizes. The system can handle various PU sizes (64×64, 32×32, 16×16, etc.) using a unified hierarchical approach, maintaining operational simplicity while optimizing performance for each case through appropriate levels of subdivision.
Data Source
AI summary
A motion compensator includes a divider, a frame memory transfer controller, and a motion compensation processor. Based on information about a coding unit CU and prediction unit PU provided by a decoder, the divider determines whether or not to divide the PU. Next, based on a motion vector of the PU yet to be divided, reference image information, and information about divided blocks locations, the frame memory transfer controller determines the storage location of the reference image of a reference picture in a frame memory on the basis of each of the blocks divided, thereby obtaining reference image data. The motion compensation processor performs motion compensation operation on a motion compensation control block basis to generate a predicted image. Then, a reconstructor obtains a restored image based on a residual image generated by an inverse frequency transformer.