Solid State Image Device Narrow Wiring Section
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Solution Overview
Problem
Existing solid state image devices face image quality degradation due to the impact of analog-to-digital conversion and digital circuit operations, which is not adequately addressed by mere reductions in wiring resistance.
Innovation Solution
A solid state image device design featuring a unique wiring structure with a narrower second wiring section facing the analog-to-digital conversion and digital circuit units, reducing parasitic capacitance and minimizing the impact of these operations on image quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the wiring width is reduced to minimize parasitic capacitance, then image quality is improved, but wiring resistance increases
Solution Approach 1:
The patent applies different wiring widths in different regions: a first wiring section with width W1 over the pixel unit, a second wiring section with narrower width W2 over the analog-to-digital conversion and digital circuit units, and a third wiring section with width W3 connected to the electrode pad. This local differentiation reduces parasitic capacitance in the critical region while maintaining adequate current carrying capacity in other regions.
2Device complexity
If the wiring structure is simplified to reduce manufacturing complexity, then manufacturing cost is reduced, but image quality degradation from digital circuits cannot be suppressed
Solution Approach 1:
The patent introduces a localized structural variation (narrower second wiring section) specifically over the analog-to-digital conversion and digital circuit units to reduce parasitic capacitance and its harmful effects on image quality, while keeping the overall wiring structure relatively simple and manufacturable.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively suppresses image quality degradation by reducing parasitic capacitance and variations in ground potential, leading to improved image capture results.
Implementation Method 1
A solid state image device design featuring a unique wiring structure with a narrower second wiring section facing the analog-to-digital conversion and digital circuit units, reducing parasitic capacitance and minimizing the impact of these operations on image quality
Data Source
AI summary
A solid state image device includes a pixel unit including a plurality of pixels arranged in a matrix; an analog-to-digital conversion unit that converts a signal from the pixel unit into a digital signal; a digital circuit unit that processes the digital signal from the analog-to-digital conversion unit; and a wiring that supplies a predetermined voltage to the pixel unit. The wiring includes a first wiring section facing the pixel unit, a second wiring section facing at least one of the analog-to-digital conversion unit and the digital circuit unit, and a third wiring section connected to an electrode pad and connected to an electrode pad and between the second wiring section and the electrode pad, and the width of the second wiring section is smaller than respective widths of the first wiring section and the third wiring section.