Image Dividing Circuit Pixel Allocation for Frame Rate Synchronization
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Solution Overview
Problem
Existing image dividing circuits face challenges in synchronizing frame rates when the total number of horizontal pixels in the input image data is not divisible by the number of display drivers, leading to display errors due to mismatched horizontal scanning periods.
Innovation Solution
An image dividing circuit that variably adjusts the total number of horizontal pixels and vertical lines in each channel to ensure that the data output rate per channel is 1/n of the data input rate, using a frequency dividing circuit to generate a pixel clock signal with a frequency 1/n of the input pixel clock signal, and an adjustment circuit to synchronize frame rates by controlling the number of pixels and lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the total number of horizontal pixels is divided equally among n display drivers, then the horizontal resolution per driver is optimized, but frame rate synchronization is lost when the total horizontal pixels is not an integer multiple of n
Solution Approach 1:
The patent dynamically adjusts the horizontal pixel allocation parameters for each display driver based on the remainder value. When the total horizontal pixels HT is not divisible by n, the system calculates the remainder and redistributes pixels accordingly - some drivers receive HT//n pixels while others receive HT//n + 1 pixels. This parameter adjustment maintains both resolution optimization and frame rate synchronization.
Solution Approach 2:
The patent implements a dynamic pixel distribution mechanism that adapts to different input resolutions. The system calculates the remainder of HT divided by n and dynamically adjusts the pixel allocation for each driver. This dynamic approach allows the system to handle various scenarios (remainder 0, 1, 2, etc.) and maintain synchronization while optimizing resolution distribution.
2Reliability
If the horizontal scanning period is adjusted to match input data, then frame rate synchronization is achieved, but the horizontal resolution per driver decreases
Solution Approach 1:
The patent changes the pixel allocation parameters for each driver based on the remainder calculation. Instead of uniformly allocating HT//n pixels to all drivers, the system assigns HT//n + 1 pixels to some drivers and HT//n pixels to others, optimizing the total utilization while maintaining synchronization. This parameter optimization resolves the contradiction between synchronization and resolution.
Solution Approach 2:
The patent applies different pixel allocation strategies to different display drivers based on their specific channel assignments. Some drivers receive more pixels (HT//n + 1) while others receive fewer (HT//n), creating a non-uniform but optimized distribution. This local differentiation allows the system to maintain both synchronization and optimal resolution utilization.
3Productivity
If n display drivers are used to drive high horizontal resolution panels, then the driving capability is enhanced, but the complexity of synchronizing frame rates increases when HT is not an integer multiple of n
Solution Approach 1:
The patent implements a self-service synchronization mechanism where the system automatically calculates the remainder of HT divided by n and autonomously adjusts the pixel allocation for each driver. The calculation unit and control logic enable the system to self-regulate the pixel distribution without external intervention, simplifying the synchronization process while maintaining multi-driver capability.
Solution Approach 2:
The patent incorporates a feedback mechanism where the system continuously monitors the relationship between total horizontal pixels HT and the number of drivers n, calculates the remainder, and adjusts pixel allocation accordingly. This feedback loop ensures that the system maintains optimal synchronization and resolution distribution adaptively, reducing the perceived complexity for the user.
Data Source
AI summary
An image dividing circuit includes an input interface circuit that receives input image data configured by a total number of horizontal pixels HT, an image data dividing circuit that divides the input image data into first to n-th output image data, and an output interface circuit that includes output circuits for first to n-th channels that output the first to n-th output image data. The parameter n is an integer greater than or equal to 3, and the parameter HT is not an integer multiple of the parameter n. An output circuit for an i-th channel outputs i-th output image data in which at least one of the total number of horizontal pixels and the total number of vertical lines in the i-th channel has been variably adjusted. The parameter i is an integer greater than or equal to 1 but smaller than or equal to n.