Image Encoding Device Buffer Register CPU Load Reduction
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Solution Overview
Problem
Existing image encoding/decoding devices face high CPU load and long initial setting times due to the need for direct CPU intervention in setting multiple registers, especially when switching encoding/decoding processes or algorithms frequently, which is not efficiently addressed by prior techniques.
Innovation Solution
An image encoding/decoding device with a first circuit for receiving control information from the CPU and a second circuit that reads and transfers initial setting information to image processing modules, reducing the need for direct CPU intervention and DMA transfer requirements, allowing for local address mapping and efficient data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the CPU sets each register one by one utilizing slave access, then the initial setting can be completed, but the initial setting operation takes a long time and CPU load increases
Solution Approach 1:
The patent introduces a buffer register as an intermediary between the CPU and the multiple registers. The CPU writes initial setting data to the buffer register once, and then a transfer mechanism automatically distributes this data to the target registers. This mediator approach eliminates the need for the CPU to individually access each register through slave access, significantly reducing both initial setting time and CPU load.
2Adaptability or versatility
If the number of registers increases to support multi-codec processing, then the device functionality improves, but the data amount to be set becomes enormous and CPU load increases
Solution Approach 1:
The patent segments the register setting process into two independent parts: (1) The CPU sets initial data to the buffer register only once, and (2) A transfer mechanism automatically distributes this data to multiple target registers. This segmentation allows the system to support multiple codecs and numerous registers without proportionally increasing CPU load, as the CPU is involved only in the first segment while the second segment is handled automatically.
3Productivity
If DMA transfer is used to reduce CPU load, then CPU load reduction is achieved, but address space mapping complexity increases and storage circuit requirements increase
Solution Approach 1:
The buffer register serves as a mediator that simplifies the transfer mechanism. Instead of requiring complex DMA address space mapping and large storage circuits, the system uses the buffer register as an intermediate storage point. The CPU writes to this single buffer location, and the transfer mechanism handles the distribution to multiple registers, achieving CPU load reduction without the complexity of full DMA implementation.
Data Source
AI summary
An image encoding/decoding device includes a first circuit and a second circuit for providing initial setting to image processing modules. The image encoding/decoding device does not receive information, which is initially set to the image processing modules, directly from an external CPU, and control information for the initial setting is set to the first circuit from the CPU. The second circuit reads in initial setting information and setting-target information of the initial setting information from outside using the control information set in the first circuit and transfers the initial setting information to an image processing module according to the setting-target information. The CPU does not need to set the whole information, which is initially set to the image processing modules, directly to the image encoding/decoding device, and also does not need to set both a transfer source address and a transfer destination address as in DMA transfer.