Image Forming Apparatus Parallel Band Processing

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Solution Overview

Problem

Image forming apparatuses face challenges in reducing memory size and processing speed due to high resolution requirements, with existing methods causing delays in memory allocation and compression/decompression processes.

Innovation Solution

The apparatus employs a CPU, memory device, and compression/decompression processor that decompresses, rasterizes, and compresses bitmap data in parallel, using multiple data areas to manage bands of data independently, allowing for continuous processing and reduced memory requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If compressed data are stored in a hard disk drive instead of memory to reduce memory size, then memory size is reduced, but processing speed is decreased due to sequential compression and decompression

Engineering Contradiction:
Improvememory sizeVSAvoidprocessing speed
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The patent divides the page into multiple bands and processes each band independently through separate tasks. This segmentation allows parallel processing of different bands, where one task compresses data for band N while another task decompresses data for band N+1, eliminating the sequential bottleneck and enabling simultaneous compression and decompression operations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements continuous useful action by ensuring that compression and decompression operations overlap in time across different bands. While one band is being compressed, another band is being decompressed, maintaining continuous productive work without idle waiting periods. This is achieved through multiple concurrent tasks that operate on different bands simultaneously.

Inventive Principle:
Principle #20Continuity of useful action

2Productivity

If garbage collection is performed in waiting time of print data transmission to reduce memory allocation delays, then memory allocation efficiency is improved, but processing may be delayed if garbage collection takes long time

Engineering Contradiction:
Improvememory allocation efficiencyVSAvoidprocessing delay
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent performs garbage collection in advance during waiting periods before print data transmission or processing tasks begin. By proactively collecting garbage and freeing memory during idle times, the system ensures that memory is available when needed without causing delays during critical processing operations. This preliminary action prevents memory allocation delays while minimizing impact on processing throughput.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If multiple hardware RIPs operate in parallel to process at high speed, then processing speed is improved, but device complexity increases

Engineering Contradiction:
Improveprocessing speedVSAvoidsystem complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements dynamic task allocation and management where tasks can be created, suspended, and resumed based on system state and resource availability. The task management system dynamically adjusts the number and state of active tasks, allowing the system to achieve parallel processing effects without requiring multiple permanent hardware RIP units. This dynamic approach provides high processing speed with reduced hardware complexity.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS9202149B2Image forming apparatus
Publication Date: 2015.12.01 KYOCERA DOCUMENT SOLUTIONS INC
  • US9202149B2 patent drawing
  • US9202149B2 patent drawing
  • US9202149B2 patent drawing

AI summary

A CPU performs the steps of: (a) causing a compression/decompression processor to decompress the compressed data of one of three bands in the data area except for the first block in the band, and storing decompressed bitmap data in the data area; (b) rasterizing each of the intermediate data blocks in the band and synthesizing the rasterized data and the decompressed bitmap data in the band; and causing the compression/decompression processor to compress the synthesized bitmap data and storing the compressed data in the data area. The CPU performs the steps (a) to (c) in different respective tasks in parallel, and performs the steps (a) to (c) in the order of (a), (b) (c) for each of the intermediate code blocks in each of the bands while using the 1st to the 3rd bitmap data area in turn for each of the steps (a) to (c).