Image Processing Linebuffer Segmentation for Smaller Circuit Area
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Solution Overview
Problem
The hardware architecture of image processing systems requires a large silicon area due to the size of the linebuffer, which is not area-efficient and costly.
Innovation Solution
Implementing a system with multiple memories and multiplexers to store and select parts of image data rows, reducing the overall circuit area by dividing the data across multiple memory units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a large-sized linebuffer is used to increase throughput via parallelism, then productivity is improved, but the circuit area increases
Solution Approach 1:
The linebuffer is divided into multiple smaller memory units (first memory unit, second memory unit, third memory unit, etc.) that can be independently controlled. Each memory unit stores a portion of the pixel data, allowing the system to achieve the same buffering capacity with reduced area per unit while enabling selective access through multiplexers to maintain throughput performance.
2Reliability
If a large-sized linebuffer is used to store one row of image data, then reliability is improved, but the circuit area increases
Solution Approach 1:
The storage function is segmented across multiple smaller memory units, each handling a portion of the pixel data. This segmentation maintains data storage reliability through distributed storage while reducing the area footprint of each individual memory unit, with the controller coordinating access to ensure complete data availability.
Solution Approach 2:
The multiple memory units are designed with uniform structure and can perform the same storage function interchangeably. The controller manages which memory unit is accessed based on the required data portion, making each memory unit multi-functional in the sense that any unit can serve any data storage role, thereby maintaining reliability while optimizing area usage.
Data Source
AI summary
An object is to provide an information processing apparatus capable of reducing a circuit area. An information processing apparatus (1) according to the present disclosure includes a plurality of memories (11A, 11B) configured to store one row of data of input image data as a whole, a plurality of multiplexers (12A, 12B) configured to select one of the memories to take a part of the one row of data from the selected memory; and a hardware controller (13) configured to select one of the memories storing the part of the one row of data.