Multi-Chip Image Processing Load Balancing for Memory Bandwidth

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Solution Overview

Problem

Multi-chip image processing systems face memory bandwidth bottlenecks due to varying computational and memory demands based on image content, leading to inefficient resource utilization and compromised throughput.

Innovation Solution

Implementing a content-agnostic algorithm early in the image processing pipeline to estimate memory bandwidth requirements, allowing for even distribution of processing tasks between chips using inter-chip connections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If image processing tasks are distributed between multiple chips, then processing capacity and functionality are improved, but memory bandwidth bottlenecks worsen due to varying computational demands

Engineering Contradiction:

Improveprocessing capacityVSAvoidmemory bandwidth efficiency

Core Design Contradiction:

ProductivityVSLoss of energy

Solution Approach 1:

The system performs preliminary analysis of image data characteristics (such as scene complexity, motion content, and object density) before distributing processing tasks. This preliminary action enables the controller to predict memory bandwidth requirements and balance the load across chips in advance, preventing bottlenecks before they occur.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The task distribution mechanism is dynamic rather than static. The controller continuously monitors image data characteristics and adjusts the distribution of processing tasks between chips in real-time based on current memory bandwidth requirements. This dynamic adaptation ensures optimal resource utilization varying computational demands.

Inventive Principle:

Principle #15Dynamics

2Measurement precision

If content-specific algorithms are used for image processing, then processing accuracy is improved, but predictability of memory bandwidth usage worsens

Engineering Contradiction:

Improveprocessing accuracyVSAvoidmemory bandwidth predictability

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system incorporates feedback mechanisms where the controller monitors actual memory bandwidth usage and processing performance, then uses this information to optimize task distribution. This feedback loop allows the system to maintain high processing accuracy while improving predictability of memory bandwidth consumption through continuous adjustment.

Inventive Principle:

Principle #23Feedback

3Speed

If each chip processes image data independently with localized sensors, then processing speed is improved, but resource utilization efficiency worsens due to memory bandwidth constraints

Engineering Contradiction:

Improveprocessing speedVSAvoidresource utilization efficiency

Core Design Contradiction:

SpeedVSProductivity

Solution Approach 1:

The system segments image data into different portions and assigns them to different chips based on predicted memory bandwidth requirements. This segmentation allows parallel processing while balancing the load, ensuring that no single chip becomes a bottleneck. The controller divides the processing workload into manageable segments that can be handled independently yet cooperatively.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system merges the processing capabilities of multiple chips into a coordinated system. The controller combines the computational resources of individual chips and manages their collaboration on image processing tasks, allowing the system to achieve higher overall resource utilization efficiency while maintaining parallel processing speed advantages.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentEP4535277B1Distributing load in a multi-chip image processing unit for processing image data into processed image data

Publication Date: 2025.12.17 AXIS

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AI summary

This disclosure relates to methods (700) systems and non-transitory computer-readable storage mediums for distributing load in a multi-chip image processing unit for processing image data into processed image data. An example method comprises receiving (S702) first image data, analysing (S704) the first image data using a first algorithm, the first algorithm performing a set number of operations for a given size of image data input to the first algorithm, and outputs at least one characteristic of the first image data; using the at least one characteristic to estimate (S706) use of memory bandwidth in the first and second chip when processing the first image data into processed image data; and distributing (S708) processing of the first image data between the first and the second chip such that the estimated use of memory bandwidth is distributed evenly.