Image Processing Memory Power Domain Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional system on chips face performance degradation due to the inability to utilize image processing memory when the image processing logic is in a power-down mode, leading to increased reliance on external memory access, which is inefficient and burdens the external memory controller.
Innovation Solution
A system on chip design where the image processing memory is included in a separate power domain from the image processing logic, allowing it to function as internal memory even when the logic is in power-down mode, with an image memory interface controlling access paths to prioritize internal memory usage and reduce external memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the image processing memory is included in the same power domain as the image processing logic, then power consumption is reduced when logic is inactive, but the memory cannot be accessed by other sub-systems when the logic is in power-down mode
Solution Approach 1:
The system divides the power domain configuration into two separate domains: the image processing logic is in a first power domain that can be independently powered down, while the image processing memory is in a second power domain that remains active. This segmentation allows the memory to be accessible by multiple sub-systems even when the image processing logic is inactive, resolving the contradiction between power efficiency and memory accessibility.
2Productivity
If external memory is used when image processing memory is unavailable, then memory capacity is sufficient, but system performance degrades due to heavy load on external memory controller
Solution Approach 1:
The image processing memory is designed to serve multiple functions and multiple sub-systems. When the image processing logic is active, the memory serves image processing tasks. When the logic is in power-down mode, the same memory becomes available to other sub-systems through the system bus. This multi-functionality eliminates the need to switch to external memory, maintaining both system performance and memory availability.
3Productivity
If image processing memory is dedicated only to image processing logic, then memory access is simple and fast, but the memory cannot be utilized when the logic is inactive leading to resource waste
Solution Approach 1:
The system implements dynamic memory allocation based on the operational state of the image processing logic. When the logic is active, it has exclusive access to the image processing memory for fast dedicated access. When the logic enters power-down mode, the memory automatically becomes accessible to other sub-systems through the system bus. This dynamic switching resolves the contradiction between dedicated fast access and resource utilization.
Data Source
AI summary
A system on chip (Soc) includes a system bus, a plurality of sub-systems, an image processing logic block, an image memory interface and an image processing memory block. The sub-systems are respectively connected to the system bus. The image processing logic block is connected to the system bus. The image processing logic block performs an image processing. The image processing logic block is included in a first power domain. The image memory interface is connected to the system bus and the image processing logic block. The image processing memory block is connected to the image memory interface. The image processing memory block is used for the image processing. The image memory interface and the image processing memory block are included in a second power domain different from the first power domain.