Image Pickup Device Floating Diffusion Cavity

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Solution Overview

Problem

Current image pickup devices face challenges in reducing diffusion layer capacitance, which hinders the improvement of conversion efficiency, despite the formation of diffusive device separation regions.

Innovation Solution

Incorporating a hermetically-sealed cavity section inside the silicon layer on the underside of the floating diffusion section and the channel body region of the transistor, eliminating the p-n junction region and thereby reducing diffusion layer capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If diffusive device separation regions are formed on either side of an FD section, then device isolation is improved, but diffusion layer capacitance remains large and conversion efficiency is not significantly improved

Engineering Contradiction:
Improvedevice isolationVSAvoidconversion efficiency
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent transitions from two-dimensional planar separation regions to three-dimensional cavity structures beneath the floating diffusion section. By forming cavities in the vertical dimension below the FD section, the patent achieves effective isolation while reducing the capacitance-forming p-n junction region, thereby resolving the contradiction between device isolation and conversion efficiency.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent extracts and removes the p-n junction region from beneath the floating diffusion section by forming cavities in that area. This extraction eliminates the source of excessive diffusion layer capacitance while maintaining device isolation through the cavity structure, thus improving conversion efficiency without sacrificing reliability.

Inventive Principle:
Principle #2Taking out (Extraction)

2Loss of energy

If a hermetically-sealed cavity section is formed inside the silicon layer on the underside of the floating diffusion section, then diffusion layer capacitance is reduced and conversion efficiency is improved, but device structure becomes more complex

Engineering Contradiction:
Improveconversion efficiencyVSAvoiddevice structure
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent segments the silicon layer beneath the floating diffusion section by forming discrete cavity structures. This segmentation approach reduces diffusion layer capacitance by removing the p-n junction region while maintaining a manageable device structure through systematic, repeatable cavity formation processes.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances the conversion efficiency of the image pickup device by minimizing diffusion layer capacitance, leading to improved performance in low illuminance conditions.

Implementation Method 1

a photodiode provided on each pixel basis to perform photoelectric conversion to generate a charge depending on the light receiving amount

Methodology Applied
Scientific EffectPhotoelectric conversion: Photoelectric Effect

Data Source

PatentUS9602746B2Image pickup device and electronic apparatus
Publication Date: 2017.03.21 SONY GROUP CORP
  • US9602746B2 patent drawing
  • US9602746B2 patent drawing
  • US9602746B2 patent drawing

AI summary

An image pickup device includes on a silicon layer: a photodiode provided on each pixel basis to perform photoelectric conversion to generate a charge depending on the light receiving amount; a floating diffusion section configured to store the charge generated by the photodiode; and a transistor configured to output a pixel signal at a voltage in accordance with a level of the charge stored in the floating diffusion section, wherein the image pickup device further includes a hermetically-sealed cavity section inside the silicon layer and on at least one of the underside of the floating diffusion section and the underside of a channel body region of the transistor.