Image Processing Pipeline External I/O Module Bus Overload
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Solution Overview
Problem
Existing image processing devices face inefficiencies due to the need for redundant data reading and increased bus bandwidth overload, particularly when performing spatial filtering across divided image regions, and lack the ability to easily extend image processing functions by integrating external modules into pipeline processing.
Innovation Solution
The image processing device incorporates an external input/output module that directly processes and transfers data without using the data bus, allowing for efficient handling of margin regions and enabling the integration of external image processing modules into the pipeline configuration, thereby reducing bus overload and enhancing processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If image processing is performed by dividing image data into multiple rectangular regions and processing each region separately, then processing efficiency is improved, but bus bandwidth overload increases due to redundant reading of margin region data
Solution Approach 1:
The patent applies preliminary action by pre-storing margin region data from adjacent blocks in buffer memory before processing each block. This allows the spatial filtering process to access required margin data without redundant bus transactions, resolving the contradiction between processing efficiency and bus bandwidth usage.
Solution Approach 2:
The patent extracts margin region data from adjacent blocks and stores it separately in buffer memory before processing. This extraction principle allows the main processing block to access margin data locally without repeatedly accessing the frame memory via the data bus, reducing bus bandwidth overload while maintaining processing efficiency.
2Productivity
If image data is divided into multiple rectangular regions for parallel processing, then overall processing speed is improved, but continuity of data flow is lost between regions requiring margin region processing
Solution Approach 1:
The patent prepares margin region data in advance by storing it in buffer memory before processing each block. This preliminary preparation ensures that data flow continuity is maintained across block boundaries without compromising the parallel processing structure, thus resolving the contradiction between processing speed and data flow continuity.
Solution Approach 2:
The patent introduces buffer memory as an intermediary between the frame memory and processing blocks. This intermediary stores margin region data locally, enabling seamless data flow between adjacent blocks while maintaining the divided rectangular region processing structure, thereby preserving both processing speed and data flow continuity.
3Adaptability or versatility
If an external image processing module is integrated into the pipeline, then processing functionality is extended, but device complexity increases
Solution Approach 1:
The patent implements a universal interface structure that allows external image processing modules to be integrated into the existing pipeline without requiring separate dedicated interfaces for each module type. This multi-functional interface design extends processing functionality while minimizing the increase in device complexity through standardized integration mechanisms.
Solution Approach 2:
The patent segments the image processing system into modular components including the frame memory, processing blocks, and external modules that can be independently configured and integrated. This segmentation allows external modules to be added to the pipeline in a structured manner, extending functionality while keeping the overall system complexity manageable through clear modular boundaries.
Data Source
AI summary
The present invention provides an image processing device in which an image processing section for configuring a pipeline by connecting a plurality of processing modules for performing predetermined processing on input image data in series performs image processing for each block obtained by dividing image data of one frame read from a data storage section via a data bus, wherein the image processing section includes an external input/output module incorporated into the pipeline as a processing module configured to perform processing different from processing of each of the processing modules and wherein the external input/output module is configured to directly transmit data from and to an external processing section outside the image processing section without involving the data bus at a position where the external input/output module is incorporated into the pipeline.