Image Processing Device Pipeline Uniform Block Segmentation
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Solution Overview
Problem
Pipeline processing efficiency decreases when applied to coding units of varying sizes due to increased processing time and idle time, as the amount of pixel data varies, leading to reduced processing efficiency and performance in image decoding devices.
Innovation Solution
An image processing device that divides the coded stream into uniform processing unit blocks, allowing each process unit to execute processes based on a standardized size, thereby reducing idle time and improving operation efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pipeline processing is applied to coding units of varying sizes, then the image decoding device can process multiple macroblocks in parallel, but the processing time becomes inconsistent across stages causing idle time and reduced efficiency
Solution Approach 1:
The patent segments the coding units into uniform processing blocks regardless of their original varying sizes. By dividing the coded stream into standardized processing units, the pipeline can process each segment in consistent time slots, eliminating idle time caused by variable processing durations of different sized coding units.
Solution Approach 2:
The patent changes the parameter of processing unit size from variable (matching coding unit sizes) to fixed (standardized blocks). This parameter change allows the pipeline processing stages to operate with consistent data volumes, ensuring equivalent processing cycles and eliminating idle time while maintaining high decoding productivity.
2Adaptability or versatility
If coding units of different sizes are used to improve compression efficiency, then the image coding can adapt to various image characteristics, but the pipeline processing efficiency decreases due to varying processing times
Solution Approach 1:
The patent maintains the adaptability of variable-sized coding units for compression efficiency while segmenting them into uniform processing blocks for pipeline operations. This dual segmentation approach allows the system to preserve coding flexibility while achieving consistent pipeline processing efficiency through standardized processing unit sizes.
Solution Approach 2:
The patent creates a universal processing block structure that can handle coding units of any size. By designing processing units with fixed dimensions that can accommodate variable-sized coding data, the system achieves both adaptability to different image characteristics and consistent pipeline processing efficiency.
3Stability of the object's composition
If the processing cycle is determined by the longest processing stage, then all stages can be synchronized, but stages with shorter processing cycles experience idle time waiting for the longest stage
Solution Approach 1:
The patent changes the processing unit size parameter to a fixed value that standardizes the data volume across all pipeline stages. This parameter change ensures that each stage processes equivalent amounts of data in uniform time slots, achieving both synchronization and eliminating idle time, thereby improving overall processing efficiency.
Solution Approach 2:
The patent creates equipotential processing conditions by standardizing the processing unit size across all pipeline stages. This ensures that each stage operates at equivalent processing capacity and time requirements, eliminating the synchronization bottleneck where shorter stages must wait for the longest stage, thus improving overall productivity.
Data Source
AI summary
Provided is an image processing device which performs plural processes efficiently, by pipelining, on a coded stream obtained by coding an image based on various coding unit blocks. The image processing device which performs plural first processes, by pipelining, on a coded stream obtained by dividing an image into plural coding unit blocks having at least two sizes, and coding the image on a coding unit block-by-block basis includes: plural first process units which perform, by the pipelining, the plural first processes on the coded stream by each executing one of the plural first processes; and a control unit which divides the coded stream into plural first processing unit blocks each having a first size, and control the plural first process units to cause the plural first processes to be executed for each of the first processing unit blocks.