Image Processing Device Block-Based Decoding and Format Conversion
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Solution Overview
Problem
Existing image processing systems face delays in format conversion, leading to inefficient decoding and processing, particularly in real-time applications like video chat and wireless displays, due to complexities in controlling picture division and memory management.
Innovation Solution
An image processing device with a decoded data memory, format-converted data memory, a decoder, and a progress notification unit allows simultaneous decoding and format conversion by transferring decoded data in blocks and using a progress signal to synchronize the format conversion process, enabling high-speed execution without delaying the decoder.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If format conversion is performed sequentially after decoding, then decoding can be completed first, but the overall processing speed decreases due to sequential execution
Solution Approach 1:
The patent segments the picture data into multiple blocks and processes each block independently through decoding and format conversion. This allows parallel processing of different blocks, improving overall processing speed while maintaining manageable control complexity through modular block-based handling.
Solution Approach 2:
The patent enables continuous processing by allowing the format conversion unit to start converting blocks as soon as they are decoded, without waiting for the entire picture to be decoded first. This overlapping execution of decoding and format conversion eliminates idle time and improves productivity.
2Reliability
If the decoder waits for format conversion to complete, then data can be processed in order, but system delays increase particularly in real-time applications
Solution Approach 1:
The patent performs preliminary format conversion on decoded blocks immediately after decoding completes, rather than waiting for the entire picture. This preliminary action on individual blocks reduces system delay while maintaining data integrity through progressive processing.
Solution Approach 2:
The patent introduces a buffer memory as an intermediary between the decoder and format conversion unit. This buffer allows the decoder to write decoded blocks independently while the format conversion unit reads and converts them at its own pace, eliminating waiting delays while ensuring data availability.
3Quantity of substance
If picture division and alternating decoding/format conversion are used, then memory capacity is reduced, but control complexity increases
Solution Approach 1:
The patent divides the picture into multiple blocks and processes them sequentially through the same decoding and format conversion pipeline. This segmentation reduces memory capacity requirements compared to storing entire pictures, while keeping control complexity manageable through uniform block-based processing.
Solution Approach 2:
The patent processes blocks progressively rather than waiting for complete picture decoding. By performing format conversion on partial data (individual blocks) as they become available, the system reduces memory requirements while maintaining acceptable control complexity through incremental processing.
Data Source
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AI summary
Signal processing including decoding and format conversion is executed on compressed image data at a high speed by simple control. A decoder decodes compressed image data in units of blocks and writes the decoded data in the blocks into a decoded data memory. A progress notification unit generates a progress signal indicating a state of progress that data is being decoded or written into the decoded data memory by the decoder and outputs the signal to a format conversion unit per picture. The format conversion unit reads out the decoded data from the decoded data memory and format-converts the data, and writes the format-converted data into a format-converted data memory. In reading out data from the decoded data memory, the format conversion unit acquires information indicating an address of decoded data readable from the decoded data memory from the progress signal.