Image Processing Circuit Asymmetric Area Division
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Solution Overview
Problem
In image processing systems, the increased data amount from high-resolution and high-frame-rate moving images can lead to memory bandwidth deficiencies, causing image loss and dropped frames during reproduction, especially when multiple image processors are involved.
Innovation Solution
An image processing apparatus with multiple image processing circuits and memories, where each circuit has a decoding unit, a determination unit to divide frame areas for processing, and a transmission unit to balance data distribution, ensuring that the first image processing circuit processes smaller areas than others to prevent memory bandwidth insufficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple image processors are used to process high-resolution and high-frame-rate moving images, then processing capability is improved, but memory bandwidth deficiency occurs causing image loss and dropped frames
Solution Approach 1:
The patent divides the image processing task into multiple independent image processors, each handling a portion of the processing workload. This segmentation allows parallel processing of high-resolution and high-frame-rate moving images, improving overall processing capability while distributing memory bandwidth requirements across multiple processors to prevent any single processor from experiencing bandwidth deficiency that would cause image loss or dropped frames
Solution Approach 2:
The patent assigns different processing responsibilities to different image processors based on their local capabilities and memory bandwidth characteristics. By optimizing the division of processing tasks according to each processor's specific properties, the system achieves improved productivity while ensuring that no single processor becomes a bottleneck that would cause image loss or frame drops
2Speed
If image processing is divided and performed by multiple image processors with equal area division, then processing speed is improved, but memory bus bandwidth becomes unbalanced causing processing delays
Solution Approach 1:
The patent implements asymmetric area division where different image processors handle different sized processing areas rather than equal division. This asymmetry balances the memory bus bandwidth utilization across processors by compensating for differences in processing capabilities and memory access patterns, preventing processing delays while maintaining high processing speed through parallel operation
Data Source
AI summary
An image processing apparatus has a plurality of image processing circuits, each having a local memory, an image processing unit, and a communication unit communicating with other image processing circuits. A first image processing circuit among the plurality of image processing circuits has a decoder which decodes encoded RAW moving image data to store the decoded RAW moving image data in the local memory, a determiner which determines areas out of the obtained frame that the plurality of image processing circuits respectively process, and a transmitter which transmits RAW image data of the determined areas to other image processing circuit. The determiner sets the size of the area in the frame that the first image processing circuit processes to be smaller than the size of area that the other image processing circuit processes.