Image Processing Device Using Color Component Sorting for HDR Data Compression
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Solution Overview
Problem
Current image processing devices face challenges in reducing the amount of image data transferred between memory and HDR image processing circuits, leading to high transmission bit rates and bottlenecks in dynamic range expansion, higher resolution, and frame rate, while increasing storage capacity or bus width is costly and complicates integration with system-on-chip.
Innovation Solution
An image processing device that compresses image data by sorting pixels into lines corresponding to color components, stores the compressed data, and then expands and interpolates it to generate composite images with expanded dynamic range, reducing data transfer and bit rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the storage capacity of the frame memory is increased, then the dynamic range and resolution of the HDR image can be expanded, but the cost increases
Solution Approach 1:
The imaging area is divided into a first imaging area and a second imaging area. The first imaging area captures images at normal exposure for standard dynamic range requirements, while the second imaging area captures images at varied exposure levels for high dynamic range composition. This segmentation allows HDR processing to be performed only on the second imaging area, reducing the overall data storage and processing requirements while maintaining expanded dynamic range and resolution where needed.
Solution Approach 2:
Different imaging qualities are applied to different regions of the image sensor. The first imaging area uses standard imaging parameters suitable for normal scenes, while the second imaging area uses HDR imaging parameters for scenes requiring extended dynamic range. This local differentiation optimizes resource allocation, reducing memory capacity requirements and cost while maintaining high quality where necessary.
2Productivity
If the frequency of the transfer clock signal is raised, then the transmission bit rate increases to eliminate bottlenecks, but the cost increases
Solution Approach 1:
The image data is segmented into data from the first imaging area and data from the second imaging area. Only the data from the second imaging area, which requires HDR processing, is transferred at high bit rates. The data from the first imaging area can be processed separately or transferred at lower bit rates, thereby achieving the necessary transmission performance without requiring the entire system to operate at high cost.
Solution Approach 2:
Instead of transferring all image data at maximum bit rate, the invention applies partial action by transferring only the necessary HDR data from the second imaging area at high bit rate, while handling the first imaging area data more efficiently. This eliminates transmission bottlenecks for critical data without incurring the cost of raising the transfer clock frequency for the entire data stream.
3Productivity
If the width of the bus line of the frame memory is increased, then the transmission bit rate increases to eliminate bottlenecks, but the cost increases
Solution Approach 1:
The bus line bandwidth is allocated segmentally based on the imaging area. The second imaging area, which generates HDR data requiring high transmission bit rate, is assigned sufficient bus width. The first imaging area, generating standard dynamic range data, uses a narrower bus allocation. This segmented bandwidth allocation achieves the necessary transmission performance for HDR processing without the cost of increasing the overall bus line width.
4Device complexity
If HDR image processing circuit is incorporated in system-on-chip, then integration is achieved, but memory capacity and internal bus frequency become restricted
Solution Approach 1:
The system-on-chip is designed with segmented memory allocation and processing pipelines. The first imaging area data and second imaging area data are processed through different pathways within the SoC. The HDR processing circuit receives data only from the second imaging area, allowing it to operate with optimized memory capacity and bus frequency allocations that would be insufficient if the entire image sensor output were routed through HDR processing.
Data Source
AI summary
An image processing device includes a compression circuit adapted to perform compression of image data after sorting the pixels in an arrangement included in a plurality of lines in image data into a plurality of lines corresponding respectively to color components, a memory adapted to store the image data thus compressed, and an expansion circuit adapted to expand the image data thus compressed to restore the arrangement of the pixels.