Image Processing Path Throughput via Dual Buffer Tiling

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Multifunction xerographic systems with Software Image Path (SWIP) processing and without dedicated Electronic Pre-Collation (EPC) memory face challenges in maximizing throughput due to real-time memory allocation overhead, which affects performance in high-speed color reproduction.

Innovation Solution

The system allocates physical memory into two buffers and divides digital images into tiles, using Direct Memory Access (DMA) to decompress and process image data in parallel, optimizing memory usage and processing efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If controller interrupts are used for dynamic memory allocation in real time, then memory allocation flexibility is improved, but processing overhead increases and throughput decreases

Engineering Contradiction:
Improvememory allocation flexibilityVSAvoidprocessing throughput
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The image data is divided into multiple tiles, and memory is allocated in discrete block units. This segmentation allows the system to allocate memory in manageable chunks without requiring continuous controller intervention, reducing overhead while maintaining flexibility.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Memory blocks are pre-allocated and organized in a structured format before processing begins. The system prepares memory allocation patterns in advance, eliminating the need for real-time controller interrupts during actual image processing, thus improving throughput while preserving allocation flexibility.

Inventive Principle:
Principle #10Preliminary action

2Speed

If dedicated Electronic Pre-Collation (EPC) memory is used, then processing speed is improved, but device cost and complexity increase

Engineering Contradiction:
Improveprocessing speedVSAvoidmemory architecture complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent uses general-purpose physical memory with buffer structures to perform functions traditionally requiring dedicated EPC memory. By making the memory system multi-functional and reusable across different operations, the system achieves high processing speed without the cost and complexity of dedicated hardware memory.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system optimizes processing speed by changing memory access patterns and organization rather than using dedicated EPC hardware. Through parameter optimization in software-controlled memory management, the system achieves EPC-like performance using standard memory components.

Inventive Principle:
Principle #35Parameter changes

3Quantity of substance

If compression is applied to image data, then memory usage is reduced, but decompression overhead increases processing time

Engineering Contradiction:
Improvememory usageVSAvoiddecompression time
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

Compressed image data is divided into tiles that can be decompressed in parallel. This segmentation allows the decompression overhead to be distributed across multiple processing units or time slots, reducing the impact on overall processing time while maintaining efficient memory usage through compression.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9928187B2Increasing data throughput in the image processing path of a document reproduction device
Publication Date: 2018.03.27 XEROX CORP
  • US9928187B2 patent drawing
  • US9928187B2 patent drawing
  • US9928187B2 patent drawing

AI summary

What is disclosed is a system and method for increasing throughput in the image processing path of a digital document reproduction device. A digital image to be processed is received. Memory is allocated into two buffers, B[0] and B[1]. Each buffer has sizeSB≤M2,where M is a size of the allocation. The digital image is divided into N number of tiles. Then, for tiles Ti, where i=1 to N: (A) the image data of tile Ti is decompressed into buffer B[((i% 2)=0], and (B) the image data of buffer B[(i% 2)≠0] is decompressed into the image path pipeline. Send a signal indicating that processing of the digital image has completed.