Image Processing Apparatus FIFO Buffer Configuration
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Solution Overview
Problem
Existing image processing apparatuses face inefficiencies in changing the number of channels of the Direct Memory Access (DMA) controller (DMAC) when modifying the window size, which affects processing speed and image quality.
Innovation Solution
The image processing apparatus incorporates a processor with a reading DMAC and a writing DMAC, along with upper and lower FIFO units, allowing for the modification of the number of input lines to the processor without altering the number of channels of the DMAC, by using a specific ratio of FIFOs in the lower FIFO unit corresponding to those in the upper FIFO unit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of channels of the DMAC is changed to modify the window size, then the image quality control is improved, but the processing time increases due to configuration changes
Solution Approach 1:
The patent pre-configures multiple FIFO units with different depths (e.g., 4K, 2K, 1K, 512 bytes) before runtime. When window size needs to be adjusted, the system simply activates or deactivates pre-configured FIFO units rather than dynamically allocating memory, eliminating configuration overhead and enabling rapid window size changes.
Solution Approach 2:
The system dynamically selects which FIFO units to activate based on the required window size. By enabling or disabling specific FIFO units (e.g., activating only 1K FIFO for small windows, or combining 4K+2K+1K for large windows), the system achieves flexible window size adjustment without physical reconfiguration of the DMAC channels.
2Productivity
If the DMAC configuration is modified to adjust the number of input lines, then the processing capability is improved, but the system complexity increases
Solution Approach 1:
The patent divides the buffer memory into multiple independent FIFO units with fixed depths (4K, 2K, 1K, 512 bytes). Each FIFO unit is independently controlled and can be activated or deactivated based on processing requirements. This segmentation allows the system to achieve variable buffer capacities (e.g., 4K, 3K, 2K, 1K, 512 bytes) by combining or excluding specific FIFO units, simplifying the control logic compared to dynamic memory allocation.
Solution Approach 2:
The multiple FIFO units are designed with uniform interfaces and control mechanisms, allowing them to serve multiple purposes. The same FIFO units can be used for different window sizes, and the system can flexibly combine them to meet various buffer capacity requirements without needing separate configurations for each scenario.
Data Source
AI summary
An image processing apparatus includes a processor configured to process an image; a reading direct memory access controller (DMAC) configured to read data from the memory; a writing DMAC configured to write data to the memory, each DMAC configured to control direct memory access to a memory; an upper first-in first-out (FIFO) unit connected to the reading and writing DMACs and includes FIFOs of the number equal to the number of channels of each of the reading and writing DMACs and a lower FIFO unit connected between the upper FIFO unit and the processor and includes FIFOs that correspond to the FIFOs of the upper FIFO unit at a ratio of 1 upper FIFO unit to F lower FIFO units (F being an integer equal to 2 or larger).