Image Processing Circuitry Follower Mode for Display Sync
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Solution Overview
Problem
The synchronization of image data between integrated and external displays is challenged by clock signal drift, leading to unsynchronized presentation on external displays.
Innovation Solution
The image processing circuitry operates as a follower of the external display, utilizing a follower-go signal during a Vertical Idle state to synchronize clock signals across multiple external displays, and employs techniques like rounding clock signals based on configurable bits to ensure synchronized display.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the image processing circuitry operates independently with its own clock signal, then processing speed and autonomy are improved, but synchronization with external displays deteriorates due to clock drift
Solution Approach 1:
The image processing circuitry dynamically switches between operating modes: it can operate autonomously using its own common clock signal for high-speed processing, or it can switch to follower mode where it synchronizes to the external display's clock signal to maintain synchronization reliability. This dynamic adaptability resolves the contradiction between speed and synchronization.
Solution Approach 2:
The system changes the clock signal parameter by accepting an external clock signal from the display when synchronization is required, rather than using its internal common clock signal. This parameter change allows the image processing circuitry to align its operating frequency with the external display, eliminating drift while maintaining operational effectiveness.
2Reliability
If the image processing circuitry waits for follower-go signal during Vertical Idle state, then synchronization with external display is improved, but processing throughput may be reduced
Solution Approach 1:
The system uses periodic Vertical Idle states in the display refresh cycle as opportunities to exchange synchronization signals (follower-go signals) between the image processing circuitry and external display. By confining synchronization activities to these periodic intervals rather than continuously interrupting processing, the system maintains synchronization reliability while minimizing impact on overall processing throughput.
3Adaptability or versatility
If multiple display pipelines are used to drive different external displays, then display versatility is improved, but clock signal synchronization becomes more complex
Solution Approach 1:
The system segments the display output by using separate display pipelines for different external displays, allowing each pipeline to independently synchronize with its connected display's clock signal. This segmentation enables versatile multi-display configurations while managing synchronization complexity through modular, independent pipeline operation rather than attempting to synchronize all displays through a single complex timing system.
Data Source
AI summary
An electronic device may include a display and image processing circuitry. The image processing circuitry may receive a frame of image data for display by the display and at least one external display coupled to the electronic device, where the frame of image data comprises an active portion and an idle portion, wherein the active portion comprises data for presenting one or more images via the display and the at least one external display, receive a signal from a controller during the idle portion of the frame of image data, and initiate processing of a first line of active portion in response to receiving the signal. In this way, the frame of image data being displayed by the display and the at least one external display may be in sync.