Image Processing Apparatus Line Buffer Read Timing Control

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Solution Overview

Problem

Conventional image processing apparatuses experience delays due to memory write operations, which form a bottleneck in image processing operations, especially in video-conference systems where large amounts of image data need to be processed and transmitted in real time.

Innovation Solution

An image processing apparatus that dynamically controls read timing based on the number of lines required for image processing operations, allowing for variable read timings tailored to the specific characteristics of each operation, thereby reducing the bottleneck caused by I/O operations for memory.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a frame buffer is used to process image data frame by frame, then image processing operations can be executed, but transmission delay increases due to waiting for frame buffer filling

Engineering Contradiction:
Improveimage processing completionVSAvoidtransmission delay
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent segments the frame buffer into multiple line buffers, allowing processing to occur on a per-line basis rather than waiting for entire frames. This segmentation enables overlapping of memory write operations and processing operations, reducing transmission delay while maintaining processing reliability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements preliminary action by pre-allocating line buffers and preparing processing pipelines before actual image data arrives. This allows the system to immediately process lines as they are written to memory without waiting for frame completion, thereby reducing transmission delay.

Inventive Principle:
Principle #10Preliminary action

2Adaptability or versatility

If a frame buffer is provided to accommodate the largest required amount of data, then various image processing operations can be supported, but memory usage and processing delay increase

Engineering Contradiction:
Improveimage processing operation supportVSAvoidprocessing delay
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent dynamically adjusts the number of line buffers allocated based on the specific image processing operation being performed. Different operations require different amounts of buffer memory, and the system adapts by allocating only the necessary number of line buffers for each operation type, reducing unnecessary memory usage and processing delay.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of buffer size dynamically according to the processing operation. Instead of using a fixed large frame buffer for all operations, the system adjusts the buffer configuration to match the specific requirements of each operation (e.g., rotation, scaling, distortion correction), optimizing both memory efficiency and processing speed.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If I/O operations for memory are performed to fill the frame buffer, then image processing can be executed, but a bottleneck is formed in the processing pipeline

Engineering Contradiction:
Improveimage processing throughputVSAvoidI/O operation complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent ensures continuity of useful action by allowing memory write operations and processing operations to proceed simultaneously on different line segments. Instead of sequential execution where processing waits for complete memory filling, the system maintains continuous processing flow by operating on available data, eliminating idle time and reducing I/O bottlenecks.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS8976222B2Image processing apparatus and image processing method
Publication Date: 2015.03.10 RICOH CO LTD
  • US8976222B2 patent drawing
  • US8976222B2 patent drawing
  • US8976222B2 patent drawing

AI summary

An image processing apparatus includes an image processing command input section to receive image processing commands for image data written into a memory by units of one line, a line number deriving section to derive a number of lines of the image data required to execute image processing operations based on the image processing commands received by the image processing command input section, a line number indicating section to output a numerical value indicating the number of lines of the image data derived by the line number deriving section, a read timing controlling section to control read timing from the memory in response to the numerical value output from the line number indicating section, a parameter indicating section to output parameters used for the image processing operations, and an image processing section to execute the image processing operations.