Image Processing Apparatus Line Interleaving Controller
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Solution Overview
Problem
Existing image processing systems face delays and inefficiencies in processing image data from multiple sensors, particularly due to the need for multiple image signal processors or the limitations of processing frame data as a whole unit, which can lead to increased semiconductor device usage and area requirements.
Innovation Solution
An image processing apparatus that divides frame data into line data and performs image processing through time division multiplexing using a single image signal processor, incorporating synchronizers, a memory, and a line interleaving controller to manage and process the line data efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple image signal processors are used to process image data from multiple image sensors, then processing capability is improved, but device complexity and area occupied by semiconductor devices increase
Solution Approach 1:
The patent segments frame data into multiple line data units and processes them through time division multiplexing with a single image signal processor. This allows one processor to handle multiple image sensors by dividing the processing task into sequential line-based operations, eliminating the need for multiple processors while maintaining processing capability.
Solution Approach 2:
The patent implements periodic action through time division multiplexing, where the single image signal processor alternates between processing line data from different image sensors in sequential time slots. This periodic switching enables one processor to service multiple sensors effectively, reducing processor count while preserving processing throughput.
2Device complexity
If frame data is processed as a whole unit, then processing simplicity is maintained, but processing delays increase
Solution Approach 1:
The patent divides complete frame data into smaller line data units, allowing the image signal processor to handle and output processed data more frequently. This segmentation reduces the time each processing task must hold the processor, thereby reducing overall processing delay while maintaining systematic processing through the time division multiplexing framework.
3Area of stationary object
If a single image signal processor is used to process data from multiple image sensors, then semiconductor device area is reduced, but processing delays increase
Solution Approach 1:
By segmenting frame data into line data units, the patent enables the single image signal processor to complete and output processing results more frequently. This reduces the effective processing time per sensor while still utilizing time division multiplexing to serve multiple sensors, thereby reducing overall processing delay despite using only one processor.
Solution Approach 2:
The patent employs periodic action through time division multiplexing, where the single processor alternates between multiple sensors in defined time slots. This periodic switching pattern ensures that each sensor receives timely processing attention, reducing idle time and overall processing delay while maintaining the benefit of using only one processor and thus minimizing semiconductor device area.
Data Source
AI summary
An image processing apparatus and electronic device including the same are provided. The image processing apparatus includes a synchronizer configured to receive first frame data and second frame data, which is different from the first frame data, from an image sensor, a memory configured to receive at least part of the first frame data and at least part of the second frame data from the synchronizer and storing to store the received first frame data and the received second frame data, a line interleaving controller configured to output first line data, which is included in the first frame data stored in the memory, and second line data, which is included in the second frame data stored in the memory, through time division multiplexing, and an image signal processor configured to perform image processing, in units of lines, on the first line data and the second line data output by the line interleaving controller.