Image Processing Apparatus Memory Bandwidth Allocation
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Solution Overview
Problem
High-resolution and high-frame-rate image processing requires significant memory bandwidth, which is restricted by the slow growth of memory technologies like DRAM, making it difficult to utilize all image processing functions, especially when multiple chips are involved, as existing methods either complicate layout processing or lead to uneven memory bandwidth distribution.
Innovation Solution
An image processing apparatus with multiple units and control mechanisms that divide and combine image data across multiple chips, dynamically allocating memory bandwidth by specifying dividing positions based on storage unit usage, allowing for efficient processing without exceeding memory constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If image processing is divided into left and right images and processed by two chips, then memory bandwidth per chip is reduced by about half, but layout processing becomes complicated and memory bandwidth for overlapping regions increases
Solution Approach 1:
The image processing is segmented into multiple independent processing units (first image processing unit and second image processing unit) that operate on different portions of the image data. Each unit processes its assigned region independently, eliminating the need for complex layout processing while maintaining efficient memory bandwidth utilization.
2Device complexity
If image processing is divided into first and second halves with series connection, then layout processing is simplified, but memory bandwidth distribution becomes uneven and control difficulty increases
Solution Approach 1:
The system assigns different processing functions to different image processing units based on their capabilities and memory bandwidth characteristics. The first image processing unit handles processing requiring higher memory bandwidth, while the second unit handles other processing tasks, optimizing overall system performance and simplifying control.
3Adaptability or versatility
If multiple image processing functions are executed on a single chip, then all functions can be utilized, but memory bandwidth restriction prevents efficient processing
Solution Approach 1:
The system transitions from a single-chip architecture to a multi-chip architecture, adding a spatial dimension to the processing system. This allows multiple image processing units to operate in parallel across different chips, each with its own memory resources, thereby overcoming the memory bandwidth limitation of a single chip while maintaining functional versatility.
Data Source
AI summary
An image processing apparatus of the technique of this disclosure includes processing units, storage units, a control unit, dividing units which divide image data, and combining units which combine image data. The control unit specifies processing for which image data is divided according to a status of use of the storage units. The control unit causes one of the image processing units to process one of parts of image data divided based on a dividing position, combines the processed part of image data with the other part of image data, causes the other of the image processing units to process the other of parts of image data, the other of parts of image data being not processed by the one of the image processing units, and combines the processed part of image data with the one part of image data.