Image Processing Memory Optimization via Iterative Block Analysis
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Solution Overview
Problem
Digital cameras face increased memory requirements due to the need for storing delay lines, which leads to larger and more expensive devices, and existing methods to reduce on-chip memory either rely on external memory or increase processing time.
Innovation Solution
A method and apparatus that processes pixel blocks using reconstructed or processed data from previous lines, eliminating the need for delay lines by using iterative calculations and storing processed results, allowing for efficient image processing without external memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If delay lines are used to store image data for processing, then image processing capability is improved, but on-chip memory requirements increase
Solution Approach 1:
The patent extracts the delay line storage function from the on-chip memory by using external memory resources. The system processes image data in vertical stripes and uses external memory to store the delay lines, thereby reducing on-chip memory requirements while maintaining image processing capability through the external memory buffer.
Solution Approach 2:
The patent transitions from storing complete image lines in on-chip memory to storing only processed pixel blocks in external memory. This dimensional change in storage strategy allows the system to reduce on-chip memory usage by processing data in smaller vertical stripe units and using external memory for the delay line storage function.
2Quantity of substance
If external memory is used to reduce on-chip memory, then on-chip memory requirements decrease, but processing time increases
Solution Approach 1:
The patent segments the image processing into vertical stripe units and processes them in batches. By dividing the image into manageable vertical stripes and processing them sequentially with batched memory operations, the system reduces on-chip memory requirements while minimizing processing time through efficient stripe-by-stripe processing rather than line-by-line processing.
3Quantity of substance
If delay lines are reduced, then on-chip memory decreases, but data availability for processing is reduced
Solution Approach 1:
The patent performs preliminary processing of vertical stripe units before they are fully transferred to external memory. By pre-processing complete vertical stripes and storing only the processed results in external memory, the system ensures data availability for subsequent processing while reducing on-chip memory requirements. The preliminary action of processing entire stripes before storage maintains data integrity and availability.
Data Source
AI summary
A method and digital camera avoiding the use of delay lines for block processing within the camera, such as compressing images, demosaicing, or the like. Processing is done for a block comprising a single newly received line, together with previously acquired information. In one preferred embodiment, the block processing is performed for the single line using previous lines as retrieved from the results of previous processing. In another embodiment, the processing results for the current block are determined by the processing results of the previous block together with the newly received line. Saving delay lines provides for lower memory requirements, and enables the production of smaller and lower cost cameras.