Multi-Circuit Image Processing with Dedicated Memory Segmentation

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Solution Overview

Problem

Processing multiple image data items with integrated circuits can lead to increased processing time due to additional image processing requirements and memory access concentration issues when shared memory is accessed by multiple circuits.

Innovation Solution

An image data processing device with multiple integrated circuits and dedicated memories, where each circuit can perform read/write operations and direct memory access transfers between memories, allowing for parallel processing and reducing memory access concentration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If multiple integrated circuits process multiple image data items in parallel, then processing speed is improved, but memory access concentration increases causing processing capacity to decrease

Engineering Contradiction:
Improveprocessing speedVSAvoidprocessing capacity
Core Design Contradiction:
SpeedVSProductivity

Solution Approach 1:

The patent divides the memory system into multiple independent memory units (first memory, second memory, third memory) that can be independently accessed by different integrated circuits. This segmentation eliminates the bottleneck of shared memory access, allowing each integrated circuit to access its dedicated memory without contention, thereby maintaining high processing capacity while achieving parallel processing speed improvements

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If additional image processing is performed on each image data item, then image processing functionality is improved, but processing time increases causing processing capacity to decrease

Engineering Contradiction:
Improveimage processing functionalityVSAvoidprocessing capacity
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent assigns different image processing functions to different integrated circuits (first image processing circuit, second image processing circuit, third image processing circuit). Each circuit can perform additional image processing operations independently and simultaneously, eliminating sequential processing bottlenecks and maintaining high processing capacity while providing versatile image processing functionality

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent combines multiple image processing circuits and memory units into a unified parallel processing system. By merging the capabilities of multiple circuits that can operate simultaneously, the system achieves both enhanced functionality and maintained processing capacity through coordinated parallel operations

Inventive Principle:
Principle #5Merging (Combining)

3Adaptability or versatility

If multiple integrated circuits access shared memory simultaneously, then data sharing is improved, but memory access competition increases causing processing capacity to decrease

Engineering Contradiction:
Improvedata sharing capabilityVSAvoidprocessing capacity
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent segments the memory resource into multiple dedicated memory units, with each integrated circuit having its own dedicated memory (first integrated circuit has first memory, second integrated circuit has second memory, third integrated circuit has third memory). This eliminates memory access competition while maintaining data sharing capability through the serial interface that can transfer data between memories

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS8823995B2Image data processing device and image reading apparatus
Publication Date: 2014.09.02 PFU LTD
  • US8823995B2 patent drawing
  • US8823995B2 patent drawing
  • US8823995B2 patent drawing

AI summary

An image data processing device includes a first integrated circuit, a second integrated circuit, and a third integrated circuit. The first integrated circuit includes a first image processing circuit for first image processing for image data in a first memory, and a first serial interface for direct memory access transfer between the first memory and a third memory. The second integrated circuit includes a second image processing circuit for second image processing for image data in a second memory, and a second serial interface for direct memory access transfer between the second memory and the third memory. The third integrated circuit includes a third image processing circuit for third image processing for image data in the third memory, and a third serial interface for direct memory access transfer between the third memory and the first memory, and between the third memory and the second memory.