Image Processing Apparatus Non-Adjacent Pixel Convolution

The patent segments the feature image into multiple blocks and processes them independently. Each block can be processed with its own memory access pattern, allowing non-sequential access to different blocks while maintaining efficiency within each block. This segmentation enables dilated convolution to skip feature data without requiring continuous memory addresses across the entire feature image.

The patent transforms the one-dimensional memory access sequence into a two-dimensional block structure. By organizing feature data into blocks with spatial coordinates, the system can access non-adjacent pixels efficiently by jumping between blocks rather than sequentially through linear memory addresses. This dimensional transformation enables efficient random access patterns required for dilated convolution.

The patent extracts and processes only the necessary feature data points for dilated convolution operations. By identifying which pixels are actually needed based on the dilation rate and convolution kernel, the system skips unnecessary feature data points. This selective extraction maintains complete feature extraction for relevant positions while eliminating wasted calculations on positions that will be skipped.

The patent applies partial action by processing only the subset of feature data that is actually needed for the convolution operation. Instead of uniformly processing all feature data, the system performs calculations only where the convolution kernel overlaps with non-zero coefficients, reducing total operations while maintaining extraction precision for the required features.

The patent performs preliminary actions by pre-organizing feature data into blocks and pre-calculating the positions of pixels that will be accessed during dilated convolution. By preparing the data structure in advance with known access patterns, the system can efficiently jump to required positions without costly runtime memory search or random access optimization. This preliminary organization mitigates the speed penalty of non-sequential access.

The patent implements dynamic memory access patterns that adapt to the specific dilation rate and convolution kernel size. The memory access strategy changes based on the operation parameters, optimizing the balance between skipping feature data and maintaining access speed. This dynamic approach allows the system to switch between different access patterns (e.g., block-based vs. stride-based) depending on the computational requirements.