Image Processing Circuit with Dynamic Pipeline Segmentation
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Solution Overview
Problem
Mobile devices face difficulties in rotating and displaying high-definition images on-the-fly due to increased bandwidth requirements and challenges in processing large images efficiently.
Innovation Solution
An image processing circuit with multiple pipelines and an enable control circuit that divides images into segments based on image size and rotation information, enabling parallel processing to manage bandwidth effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the bandwidth of the DMA controller is increased to support high-definition images, then the display resolution is improved, but the device complexity and power consumption increase
Solution Approach 1:
The image processing is divided into multiple pipelines (N pipelines where N≥2), with each pipeline processing a specific segment of the image. The enable control circuit selectively activates M pipelines (2≤M≤N) based on image characteristics, allowing high-resolution processing to be distributed across multiple simpler processing units rather than requiring a single complex high-bandwidth controller.
2Measurement precision
If the bandwidth of the DMA controller is increased to support high-definition images, then the display resolution is improved, but the power consumption increases
Solution Approach 1:
The system dynamically adjusts the number of active pipelines based on image characteristics (width, height, rotation requirements). The enable control circuit determines M pipelines to activate from N available pipelines, allowing the power consumption to be optimized by activating only the necessary number of processing units for the current image processing task rather than maintaining all pipelines in a high-power state.
3Speed
If multiple pipelines are used to process image segments in parallel, then the processing speed is improved, but the device complexity increases
Solution Approach 1:
Multiple pipelines share common control and memory resources. The enable control circuit manages N pipelines that can be selectively activated, and the system uses a unified memory interface and control logic that serves all pipelines, reducing the need for duplicate components and minimizing overall device complexity while maintaining parallel processing capability.
4Productivity
If the image is divided into segments for parallel processing, then the processing efficiency is improved, but the loss of time for image merging increases
Solution Approach 1:
The parallel processing of image segments is designed to maintain continuous useful action throughout the pipeline. Multiple pipelines process different image segments simultaneously and independently, with results that can be merged without requiring additional processing steps. The segmentation approach ensures that each pipeline works continuously on its assigned segment without idle time, and the merging operation is minimized to simple composition rather than complex processing.
Data Source
AI summary
An application processor includes an image processing circuit configured to process an image on-the-fly. The image processing circuit includes N pipelines, where N is a natural number of at least 2, and an enable control circuit configured to receive first information indicating a size of the image stored in a memory and second information indicating whether the image rotates and to enable M pipelines among the N pipelines based on the first information and the second information, where 2≤M≤N. The enabled M pipelines divide the image into M image segments and process the M image segments in parallel.