Image Processor Array for High-Throughput Driver Assistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
There is a growing need for high throughput, low footprint image processors to support camera-based driver assistance systems (DAS) and autonomous cars, which require efficient image processing capabilities for tasks like lane departure warning, automatic high-beam control, pedestrian recognition, and forward collision warning.
Innovation Solution
The development of an image processor architecture that includes an array of processing units configured to concurrently receive and process warp parameters and neighboring source pixels, calculating warp results and disparity using methods such as sum of absolute differences (SAD) calculations, with a gather unit and buffering unit to manage memory access and data retrieval efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional image processing methods are used, then processing accuracy is maintained, but processing speed and throughput are insufficient for real-time DAS applications
Solution Approach 1:
The image processor divides the image processing task into multiple segments by organizing processing units in an array structure. Each processing unit handles specific portions of the image data independently, allowing parallel execution of warp calculations and SAD computations across multiple image patches simultaneously, thereby increasing overall throughput while maintaining processing accuracy
Solution Approach 2:
The patent introduces a spatial dimension to processing by arranging processing units in a two-dimensional array that matches the image patch structure. This dimensional mapping enables simultaneous processing of multiple image patches at different spatial locations, transforming sequential processing into parallel operations and significantly reducing processing time
2Productivity
If more processing units are added to increase throughput, then processing speed improves, but device complexity and footprint increase
Solution Approach 1:
Each processing unit in the array is designed as a universal, identical module capable of performing multiple functions including warp parameter calculation, SAD computation, and disparity mapping. This uniformity allows the system to scale throughput by simply adding more identical units rather than designing increasingly complex heterogeneous processors, thereby improving productivity without proportionally increasing architectural complexity
Solution Approach 2:
The patent employs identical copies of processing units arranged in an array, where each unit is a replicated instance of the same hardware module. This copying approach enables linear scaling of throughput by adding more copies while maintaining simple, repeatable architecture that is easier to design and manufacture compared to custom complex processors
3Productivity
If parallel processing is implemented to improve throughput, then processing speed increases, but memory access complexity and data retrieval overhead increase
Solution Approach 1:
The system performs preliminary actions by pre-loading image patch data into local memory buffers before processing begins. The gather unit collects and organizes neighboring source pixels and target pixels in advance, so that when parallel processing starts, all necessary data is already positioned in accessible memory locations, reducing memory access complexity during the actual parallel computation phase
Solution Approach 2:
The patent introduces intermediate buffer memory structures that act as mediators between the image memory and processing units. These buffers temporarily store pixel data and intermediate calculation results, decoupling the complex parallel access patterns from the underlying memory system and simplifying data retrieval operations for multiple processing units
Data Source
AI summary
There may be provided a non-uniform Benes network, that may include a first Benes network portion that has a first number (k) of first inputs and k first outputs; a second Benes network portion that has a second number (j) of second inputs and j second outputs; wherein j is smaller than k; and a set of multiplexers that are coupled between a set of switches of an intermediate layer of the first Benes network portion and a first layer of the second Benes network layer.