Image Processor Complex Transfer Functions Shift Register
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Solution Overview
Problem
Image processing algorithms with complex transfer functions, such as rescaling and lens distortion correction, are typically executed by CPUs, which are less energy efficient and slower than image processors, or require separate hardware, complicating chip design and increasing costs.
Innovation Solution
Generating output code from a kernel program that allows an image processor to execute complex transfer functions using a shift-register array and execution lane array, enabling direct execution without relying on a CPU or GPU, and reducing the need for separate hardware components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If complex transfer functions are executed by CPU, then execution flexibility is maintained, but energy efficiency deteriorates and processing speed decreases
Solution Approach 1:
The patent replaces CPU-based software execution with dedicated hardware circuitry designed specifically for image processing. The hardware includes specialized components such as shift register arrays and execution lane arrays that are optimized for processing image data with complex transfer functions, eliminating the need for general-purpose CPU execution and achieving both higher speed and better energy efficiency.
Solution Approach 2:
The patent changes the execution parameters from software-based virtual execution to hardware-based physical execution. By implementing complex transfer functions directly in hardware circuits with optimized data paths and parallel processing capabilities, the system achieves fundamental performance improvements in both speed and energy efficiency compared to software execution on CPUs.
2Productivity
If separate hardware device is used for complex transfer functions, then execution performance improves, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent merges the execution of complex transfer functions into the main image processing hardware architecture rather than using separate dedicated hardware devices. The execution lane arrays and shift register arrays are integrated with the existing image processing pipeline, allowing complex transfer functions to be executed within the unified hardware structure without adding separate complex subsystems.
Solution Approach 2:
The hardware architecture is designed to be universal, where the same execution lane arrays and shift register arrays can handle both simple and complex transfer functions. This multi-functional design eliminates the need for separate specialized hardware for complex operations, reducing overall device complexity while maintaining high performance.
3Ease of manufacture
If simple integer offset transfer functions are used, then hardware implementation is simple, but algorithmic flexibility deteriorates
Solution Approach 1:
The patent implements dynamic transfer function support through hardware that can adaptively handle different types of transfer functions. The execution lane arrays can dynamically adjust their operation based on the specific transfer function being executed, supporting both simple integer offsets and complex non-integer rescaling operations through configurable hardware parameters and control logic.
Solution Approach 2:
The patent segments the transfer function execution into distinct hardware components: shift register arrays for data manipulation, execution lane arrays for computation, and control logic for coordination. This segmentation allows each component to be optimized for its specific function while collectively providing support for both simple and complex transfer functions, maintaining hardware simplicity at the component level while achieving algorithmic flexibility at the system level.
Data Source
AI summary
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for supporting complex transfer functions on an image processor. One of the methods includes traversing, by each execution lane of an image processor using a shift-register array, a respective local support region and storing input pixels encountered during the traversal into local memory of the image processor. Each execution lane obtains from the local memory of the image processor one or more input pixels according to a complex transfer function. Each execution lane computes a respective output pixel for the kernel program using one or more input pixels obtained from the local memory according to the complex transfer function.