Image Processor Execution Unit Circuit for Absolute Value Sum Operations
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Solution Overview
Problem
Traditional image processors either consume high energy due to versatile software development environments or are limited in functionality due to custom-designed fixed-function circuitry, lacking a balance between versatility and power efficiency.
Innovation Solution
An execution unit circuit for an image processor that performs absolute value and sum of absolute difference operations using a two-dimensional execution lane array and shift register array, allowing for efficient processing of image data with reduced circuitry and power consumption by executing these operations in two ALU operations instead of three, thereby improving computation efficiency and supporting versatile programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If general purpose processor with vector instruction enhancements is used, then versatile application software development platform is provided, but larger amounts of energy are consumed per unit of data during execution
Solution Approach 1:
The processor is divided into multiple execution lanes (first execution lane, second execution lane, etc.) that can operate in parallel. Each execution lane can independently execute instructions on different data elements, enabling fine-grained parallelism. This segmentation allows the system to maintain software versatility while reducing energy consumption by processing data in parallel across multiple lanes rather than sequentially on a single general-purpose core.
Solution Approach 2:
The execution lanes are configured to be selectively activated based on the instruction type and data requirements. The processor can dynamically switch between different execution lanes and instruction formats (e.g., first instruction format for scalar operations, second instruction format for vector operations) to optimize energy efficiency for each specific computational task while maintaining overall versatility.
2Use of energy by moving object
If custom designed fixed function circuitry is used, then power consumption per unit of data is reduced, but limited set of tasks that the processor is able to perform is resulted
Solution Approach 1:
The execution unit implements multiple instruction formats (first instruction format with first set of operations, second instruction format with second set of operations) that can be executed by the same execution lanes. This multi-functionality allows the processor to perform diverse tasks including scalar operations, vector operations, and custom algorithms, thereby achieving versatility without requiring separate fixed-function circuits for each task type.
Solution Approach 2:
The processor enables parameterizable configuration of execution lanes through different instruction formats and operand types. The same physical execution lane can be configured to perform different operations (e.g., addition, subtraction, multiplication) by changing the instruction format parameters, allowing flexible adaptation to various computational tasks while maintaining efficient hardware architecture.
3Reliability
If three ALU operations are used to perform SAD operation, then complete functionality is achieved, but computation efficiency is reduced
Solution Approach 1:
The patent combines multiple ALU operations into a single execution cycle by utilizing the parallel execution lanes. The first execution lane performs the absolute difference calculation while the second execution lane simultaneously performs the addition to the accumulator, merging what would traditionally be three sequential ALU operations into one parallel execution step, thereby achieving both complete functionality and improved computation efficiency.
Data Source
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AI summary
An execution unit is described. The execution unit includes an arithmetic logic unit (ALU) circuit having a first input to receive a first value and a second input to receive a second value. The ALU circuit includes circuitry to determine an absolute value of the first value and to add the absolute value to the second value. The first input is coupled to a first data path having register space and an output of another ALU of the execution unit circuit as alternative sources of the first value. The second input is coupled to a second data path having the register space as a source for the second value.