Image Processor I/O Unit Raster to Block Conversion
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Solution Overview
Problem
Traditional image processors either consume high energy due to versatile software development capabilities or lack versatility due to fixed function hardwired circuitry, failing to balance power efficiency with application software development opportunities.
Innovation Solution
An image processor architecture featuring a storage circuit, reformatting circuit, two-dimensional execution lane array, and shift register array that converts raster scan input data into block image format for efficient processing by stencil processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If general purpose processor with vector instruction enhancements is used, then versatile application software development capabilities are provided, but energy consumption per unit of data increases
Solution Approach 1:
The processor is divided into multiple execution lanes (e.g., 16 lanes) that can be selectively activated. Each execution lane contains complete processing resources (ALU, registers, etc.), allowing the system to segment the processing workload across multiple specialized units rather than using a single general-purpose core, thereby reducing energy consumption for specific image processing tasks while maintaining versatility.
Solution Approach 2:
The patent introduces a two-dimensional array of execution lanes and a two-dimensional shift register array, moving from traditional one-dimensional vector processing to two-dimensional parallel processing. This dimensional expansion enables simultaneous processing of multiple image data elements across both horizontal and vertical dimensions, improving energy efficiency through increased parallelism while maintaining software versatility through programmable control.
2Use of energy by moving object
If fixed function hardwired circuitry is used, then power consumption per unit of data is reduced, but the set of tasks the processor can perform becomes limited
Solution Approach 1:
Each execution lane in the array is designed with universal functionality, containing complete processing resources (ALU, registers, control logic) that can be programmed to perform different image processing operations. This allows the same hardware structure to be universally applied to multiple tasks (filtering, edge detection, color space conversion, etc.) while maintaining low power consumption through efficient hardware implementation, resolving the contradiction between versatility and power efficiency.
Solution Approach 2:
The processor employs dynamic configuration where execution lanes can be selectively enabled or disabled based on the specific processing task requirements. The system can adaptively adjust the number of active execution lanes and their operational modes to match the computational demands of different image processing algorithms, providing both versatility for different tasks and energy efficiency by activating only the necessary processing resources.
3Ease of operation
If raster scan format is used for input image data, then data acquisition is simplified, but processing efficiency with two-dimensional execution arrays is reduced
Solution Approach 1:
The patent incorporates a reformatting circuit that performs preliminary conversion of raster scan format data into block image format before the data reaches the two-dimensional execution lane array. This preliminary action reorganizes the data layout to match the two-dimensional processing structure, enabling efficient parallel processing across execution lanes while maintaining the simplicity of raster scan data acquisition from standard image sources.
Solution Approach 2:
The reformatting circuit acts as an intermediary between the raster scan data input and the two-dimensional execution lane array. It translates the one-dimensional raster data stream into a two-dimensional block format that aligns with the execution lane array structure, facilitating efficient data flow and processing without requiring changes to the simple raster scan acquisition mechanism.
Data Source
AI summary
An image processor is described. The image processor includes a storage circuit to store segments of input image data received in a raster scan format. The image processor further includes a reformatting circuit to convert the segments of input image data into a block image format. The image processor further includes a processor comprising a two-dimensional execution lane array and a two-dimensional shift register array. The two-dimensional shift register array is to store the input image data that has been formatted into the block image format. The execution lane array is to execute instructions that operate on the image data from the two-dimensional shift register array.