Image Processor Kernel Matrix Power Fluctuation Reduction
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Solution Overview
Problem
Existing image processing systems face challenges in efficiently processing pixel data from image sensors, particularly in reducing power fluctuations and improving data throughput, which can lead to image quality deterioration due to uneven power distribution across processing lines.
Innovation Solution
An image processing device with a first conversion unit that scans and stores pixel data in line memories, generating an M*N kernel matrix, and a second conversion unit that reorders the processed data to match the input format, allowing for even power distribution and reduced power fluctuations by processing data in units of M*N kernel matrices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If pixel data is processed sequentially line by line, then power consumption is reduced, but processing speed and data throughput deteriorate
Solution Approach 1:
The image processing device divides the pixel data processing into multiple processing units, each handling a specific portion of the kernel matrix. This segmentation allows parallel processing of different data blocks while maintaining controlled power consumption in each unit, thus improving overall processing speed without excessive power usage.
Solution Approach 2:
The patent transforms the sequential one-dimensional line-by-line processing into two-dimensional M*N kernel matrix processing. By reorganizing data in a matrix format, multiple processing units can operate simultaneously on different elements of the matrix, achieving parallel processing that improves throughput while keeping individual unit power consumption manageable.
2Productivity
If data is processed in larger blocks, then data throughput is improved, but power fluctuations increase
Solution Approach 1:
Large data blocks are divided into smaller processing units that handle specific portions of the M*N kernel matrix. Each processing unit operates independently with controlled power consumption, preventing large power fluctuations while maintaining high data throughput through parallel operation of multiple units.
Solution Approach 2:
The patent changes the processing parameter from sequential line-by-line to M*N kernel matrix blocks, optimizing the balance between throughput and power stability. By carefully selecting M and N values, the system achieves high data throughput while each processing unit consumes power within stable, fluctuation-free limits.
3Productivity
If processing is performed on the entire kernel matrix at once, then processing efficiency is improved, but hardware complexity increases
Solution Approach 1:
The kernel matrix processing is segmented into multiple processing units, each handling a portion of the matrix. This segmentation improves processing efficiency through parallel operation while avoiding the hardware complexity of a single massive processing unit, as each segment uses simpler, standardized circuitry.
Solution Approach 2:
Multiple processing units use identical, standardized circuit designs that can handle different portions of the kernel matrix. This universality allows the system to process the entire matrix efficiently through parallel operations while keeping individual unit complexity low, as each unit is a simplified, reusable module.
Data Source
AI summary
An image processor, including a first conversion unit sequentially scanning input pixel data, storing the pixel data for each line, and outputting an M*N kernel matrix through the stored pixel data, M and N being integers greater than or equal to 2, an image processing circuit image-processing pixel data corresponding to the M*N kernel matrix on a processing unit basis, and a second conversion unit reordering a result of the image-processing by the image processing circuit to correspond to a format of pixel data input to the first conversion unit and outputting the reordered result.