Image Processor Scaling Logic with Rotation Buffer
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Solution Overview
Problem
Image processors face challenges in supporting high-performance applications while minimizing power consumption, as 'on-the-fly' transformations require significant line memories and scaling ratio limitations, and deferred transformations increase overall system power consumption.
Innovation Solution
An image processor design that includes first scaling logic for horizontal scaling, a rotation buffer for storing scaled data in a rotated state, and second scaling logic for vertical scaling, allowing for efficient 'on-the-fly' rotation/scaling-down operations without increasing line memory capacity, thereby supporting both high-performance and low-power applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If image processor performs on-the-fly transformations, then power consumption is reduced, but line memory capacity and scaling ratio are limited
Solution Approach 1:
The image processor is divided into multiple functional modules: first scaling logic for horizontal scaling, rotation buffer for rotation, and second scaling logic for vertical scaling. This segmentation allows each module to operate independently with optimized memory requirements, enabling on-the-fly transformations without requiring excessive line memory capacity.
Solution Approach 2:
The patent introduces a rotation buffer that stores intermediate scaled data in a rotated state, adding a temporal dimension to the transformation process. By storing only a portion of the scaled data (second number of lines less than first number of lines) in the rotation buffer during the on-the-fly operation, the system achieves rotation and scaling without requiring full-line memory capacity for the entire image.
2Productivity
If image processor increases line memory capacity to support high-resolution displays, then transformation performance is improved, but device complexity and cost increase
Solution Approach 1:
The transformation function is segmented into three independent modules: first scaling logic, rotation buffer, and second scaling logic. Each module handles a specific aspect of the transformation, allowing the system to achieve high transformation performance without requiring a single large memory component, thus reducing device complexity.
Solution Approach 2:
The first scaling logic performs horizontal scaling on the source image data before the rotation buffer stores the intermediate results. This preliminary action reduces the amount of data that needs to be stored in the rotation buffer, enabling high-resolution display support without proportionally increasing memory capacity or device complexity.
3Productivity
If image processor uses deferred transformations, then high performance applications are supported, but power consumption increases
Solution Approach 1:
The system performs preliminary horizontal scaling in the first scaling logic before storing data in the rotation buffer, and then performs vertical scaling in the second scaling logic during the output phase. This two-stage preliminary action enables the system to support high-performance applications with on-the-fly transformations without requiring deferred transformations, thus maintaining low power consumption.
Data Source
AI summary
An image processor comprises first scaling logic that receives image data comprising a first number of lines and generates first scaled image data by scaling down the image data in a first direction, a rotation buffer that has storage capacity for storing a second number of lines less than the first number of lines and stores the first scaled image data in a rotated state, and second scaling logic that generates second scaled image data by scaling down the first scaled image data in a second direction different from the first direction.