Image Processor SRAM Reference Image Holding Unit Design
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Solution Overview
Problem
Existing image processing technologies, such as those based on H.264, face inefficiencies due to prolonged processing time and increased bus bandwidth caused by frequent access to DRAM for cache misses and format conversion requirements, especially with enhanced resolution images.
Innovation Solution
An image processor design that includes a codec processor with a reference image holding unit capable of storing a reference image with horizontally equivalent pixels to the input image and vertically larger than the motion search range, allowing for 100% cache hit ratio and eliminating the need for format conversion, thereby reducing processing time and bus bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a reference image is stored in SRAM with a size matching the motion search range, then the cache hit ratio increases, but the SRAM size and cost increase
Solution Approach 1:
The patent applies local quality by making the reference image holding unit's capacity adaptive to the specific motion search range requirements rather than uniformly sizing it for all cases. The reference image holding unit is sized to match the vertical motion search range (e.g., 16 macroblocks × 16 pixels = 256 pixels vertically) while maintaining full horizontal resolution, creating a non-square reference image region that optimizes memory usage for the actual search needs.
Solution Approach 2:
The patent changes the dimensional approach by storing reference images in a non-square format (different vertical and horizontal dimensions) rather than a square format. The reference image has horizontal pixels equal to the input image width but vertical pixels equal to the motion search range, creating a rectangular reference image region that efficiently uses SRAM capacity while covering the entire motion search area.
2Reliability
If the reference image holding unit stores the entire reference image, then the cache hit ratio reaches 100%, but the SRAM capacity requirements increase
Solution Approach 1:
The patent applies partial action by storing only the necessary portion of the reference image that falls within the motion search range. Instead of storing the entire reference image, the reference image holding unit stores a rectangular region that covers the full horizontal width but limited vertical height corresponding to the motion search range (e.g., ±8 macroblocks), which is sufficient to achieve 100% cache hit ratio for the actual search operations.
3Adaptability or versatility
If format conversion circuit is implemented to convert codec format to raster format, then display compatibility is improved, but processing time and power consumption increase
Solution Approach 1:
The patent applies preliminary action by pre-organizing the reference image data in the SRAM in a format that is directly suitable for both motion search operations and subsequent display output. The reference image holding unit stores the reference image with horizontal pixel alignment that matches the display raster format requirements, eliminating the need for post-processing format conversion and enabling direct usage for both encoding/decoding and display.
4Adaptability or versatility
If DRAM access is performed frequently for cache misses, then the reference image can be updated, but the bus bandwidth increases and processing time prolongs
Solution Approach 1:
The patent applies preliminary action by pre-loading the entire reference image (within the motion search range) into the SRAM reference image holding unit before motion search operations begin. This preliminary population of the reference image ensures that all necessary data is available in the fast SRAM memory, eliminating the need for frequent DRAM accesses during the actual encoding/decoding process and preventing cache misses.
Data Source
AI summary
The codec processor includes an SRAM that holds a reference image read from an image storage, and a motion search unit that performs motion search on the basis of a reference image held in the SRAM to generate a prediction block for a target block in an input image. The SRAM holds a reference image having a horizontally equivalent number of pixels to a horizontal number of pixels of the input image and a number of pixels vertically larger than or equal to a vertical motion search range.