Image Recognition Processor with Functional Safety Core for Error Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Advanced Driver Assistance Systems (ADAS) and autonomous driving systems require high precision and reliability in processing large amounts of sensor data in real-time, with existing pattern recognition systems lacking effective fault tolerance and error detection mechanisms, which can lead to significant accidents due to minor recognition errors.
Innovation Solution
An image recognition processor with a core array of nano cores arranged in rows and columns, utilizing independent voltage and clock regulators for a functional safety processor core to detect and tolerate recognition errors by comparing results from multiple nano core groups, ensuring fault tolerance and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a distributed computing technique using a large number of CPU cores is used for pattern recognition, then processing speed and productivity are improved, but reliability and fault tolerance deteriorate due to increased vulnerability to recognition errors
Solution Approach 1:
The processor is divided into multiple nano cores arranged in rows and columns, with each core capable of independent pattern recognition operations. The nano cores are organized into groups where each group processes data independently, allowing parallel computation while maintaining modular fault isolation.
Solution Approach 2:
Multiple nano core groups perform identical pattern recognition operations on the same input data simultaneously. Each group produces a recognition result that is then compared with results from other groups to detect and correct errors, ensuring reliability through redundant computation.
2Reliability
If multiple voltage regulators and clock generators are used for independent processor cores, then reliability and error detection capability are improved, but device complexity increases
Solution Approach 1:
The functional safety processor core is segmented into multiple independent processor units, each with its own voltage regulator and clock generator. This segmentation allows each processor to operate independently with isolated power and timing resources, enabling error detection through comparison of results from differently timed and powered operations.
Solution Approach 2:
The system incorporates redundant voltage regulators and clock generators that operate in parallel, providing a cushion against failures. By having multiple independent power and clock sources, the system can tolerate failures in individual regulators or clock generators without compromising overall functionality or reliability.
Data Source
AI summary
Provided is an image recognition processor. The image recognition processor includes a plurality of nano cores arranged in rows and columns and configured to perform a pattern recognition operation on an input feature using a kernel coefficient in response to each instruction, an instruction memory configured to provide the instruction to each of the plurality of nano cores, a feature memory configured to provide the input feature to each of the plurality of nano cores, a kernel memory configured to provide the kernel coefficients to the plurality of nano cores, and a functional safety processor core configured to receive a result of a pattern recognition operation outputted from the plurality of nano cores to detect the presence of a recognition error, and perform a fault tolerance function on the detected recognition error.