Image Scaling Circuit Reducing Interpolation Coefficients
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Solution Overview
Problem
Existing image scaling technologies in display panel drivers require significant hardware resources to feed interpolation coefficients, particularly when dealing with scaling factors that are irreducible fractions, leading to increased circuit size and processing complexity.
Innovation Solution
An image processing circuit with a scaling processing section, interpolation coefficient rearrangement section, and feeding section that selects and rearranges interpolation coefficients based on pixel coordinates, reducing the number of coefficients needed by utilizing symmetric properties in pixel arrangements to calculate pixel data for output images.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If interpolation coefficients are fed for each pixel in hardware-based image scaling, then image scaling accuracy is improved, but hardware resources and circuit size increase
Solution Approach 1:
The patent divides the image scaling process into multiple processing stages: coordinate transformation, pixel selection, and interpolation coefficient calculation. By segmenting the calculation of interpolation coefficients into reusable modules that can be shared across multiple pixels, the hardware resource consumption is reduced while maintaining scaling accuracy.
Solution Approach 2:
The patent designs universal interpolation coefficient calculation units that can serve multiple pixels. The same calculation logic and coefficient generation circuitry are reused across different pixel positions through control signals and parameter adjustments, eliminating the need for dedicated coefficient feeding circuits for each pixel.
2Measurement precision
If scaling factor is expressed as irreducible fraction M/N, then interpolation precision is improved, but number of interpolation coefficients increases
Solution Approach 1:
The patent changes the parameter representation by using the irreducible fraction M/N to generate interpolation coefficients through a systematic calculation method rather than storing all possible coefficients. The coefficients are generated on-demand using the scaling factor parameters, reducing the quantity from M×M individual coefficients to a compact set of generating parameters.
Solution Approach 2:
The patent performs preliminary calculation of base interpolation coefficients using the M/N scaling factor, then reuses these pre-calculated values through combination and transformation to derive coefficients for all pixel positions. This preliminary action reduces the total number of coefficients that need to be explicitly stored or transmitted.
3Ease of operation
If ROM is used to store interpolation coefficients, then coefficient feeding is simplified, but circuit size increases
Solution Approach 1:
The patent extracts the interpolation coefficient generation function from large ROM storage and implements it through compact calculation circuits. By taking out the coefficient data from ROM and replacing it with generation logic that computes coefficients on-demand from the scaling factor, the circuit size is significantly reduced while maintaining ease of operation through algorithmic generation.
Solution Approach 2:
The patent enables the image scaling circuit to self-generate interpolation coefficients using internal calculation units that compute coefficients from the scaling factor parameters M and N. The system serves its own coefficient needs through self-contained calculation logic rather than external ROM storage, reducing overall circuit footprint.
Data Source
AI summary
An image processing circuit includes a scaling processing section having interpolation coefficient inputs, an interpolation coefficient rearrangement section and an interpolation coefficient feeding section. The interpolation coefficient feeding section feeds first interpolation coefficients to the interpolation coefficient rearrangement section. The interpolation coefficient rearrangement section is configured to feed interpolation coefficients selected from the first interpolation coefficients and second interpolation coefficients obtained by subtracting the first interpolation coefficients from a predetermined value, respectively, to the respective interpolation coefficient inputs of the scaling processing section in response to coordinates of a target pixel of the output image. The scaling processing section is configured to generate pixel data of the target pixel of the output image by performing interpolation on the pixel data of pixels of the input image, using the interpolation coefficients fed to the interpolation coefficient inputs from the interpolation coefficient rearrangement section.