Image Sensor AD Conversion With Residual Voltage Correction
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Solution Overview
Problem
Conventional solid-state imaging devices face challenges in achieving high-speed analog-to-digital (AD) conversion while ensuring continuity of digital values, as the relationship between high-order and low-order AD converters is not adequately considered, leading to discontinuous output digital values.
Innovation Solution
The proposed solid-state imaging device incorporates a high-order AD converter and one or more low-order AD converters, along with selection circuits and a threshold voltage generation circuit, to calculate and output residual voltage values, ensuring continuity of digital values by correcting output voltages based on measured characteristics of both converters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a high-order AD converter and low-order AD converter are used to perform AD conversion at two levels, then the processing speed of AD conversion can be increased, but the output digital values become discontinuous
Solution Approach 1:
The patent applies feedback by using the output of the low-order AD converter to correct the output of the high-order AD converter. The correction unit receives both outputs and adjusts the high-order bits based on the low-order conversion result, ensuring continuity while maintaining high processing speed through the two-level conversion structure
Solution Approach 2:
The patent changes the parameter of digital value representation by introducing a correction mechanism that adjusts the high-order bits based on the low-order conversion result. This parameter change ensures that the final output maintains continuity while benefiting from the speed advantages of two-level conversion
2Productivity
If the clock frequency is increased to achieve higher-speed processing of the AD converter, then the frame rate of image output can be increased, but the power consumption of the AD converter increases
Solution Approach 1:
The patent segments the AD conversion process into two levels: high-order bit conversion and low-order bit conversion. This segmentation allows the system to achieve high frame rates without requiring extremely high clock frequencies, as each conversion stage operates independently and can be optimized for lower power consumption
Solution Approach 2:
The patent performs partial conversion at high speed (high-order bits) and completes the conversion with lower-speed processing (low-order bits). This partial action approach achieves the required frame rate without requiring the entire conversion process to operate at maximum speed, thereby reducing overall power consumption
Data Source
AI summary
A solid-state imaging device includes pixels, vertical signal lines, a high-order AD converter configured to convert M bits, a low-order AD converter, and first and second selection circuits. The first selection circuit is configured to output, in a normal mode, voltage of the selected vertical signal line and to output correction voltage in a correction mode. The high-order AD converter calculates 2M residual voltage values each corresponding to a difference between a signal voltage value and each of 2M threshold voltage values; outputs, in the normal mode, a high-order bit digital value corresponding to the maximum one of the 2M threshold voltage values in a range below the signal voltage value, and outputs voltage having a residual voltage value corresponding to the maximum threshold voltage value; and outputs, in the correction mode, voltage having a residual voltage value corresponding to a selected threshold voltage value.