AD Conversion Circuit With Unified Latch Timing for Image Sensors
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Solution Overview
Problem
Existing analog-to-digital (AD) conversion circuits in solid-state image pickup devices face accuracy degradation due to timing deviations in switching states between control signals, leading to errors in latch operations and subsequent digital data conversion.
Innovation Solution
The proposed AD conversion circuit incorporates a comparison unit, signal generation unit, latch unit, and count unit, with a control unit generating enable signals and clock signals with different phases to ensure precise timing for latch operations, using a configuration that includes NAND circuits, inverting circuits, and switch circuits to maintain consistent logic states across latch units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If separate AND circuits are used to generate control signals for different latch circuits, then the latch operations can be controlled independently, but timing deviations occur between control signals causing AD conversion accuracy degradation
Solution Approach 1:
The patent merges the control signal generation function into a single AND circuit that receives both the comparison output signal and the inverted delayed comparison output signal. This unified control signal is then distributed to multiple latch circuits, ensuring they all receive identical control timing and eliminating the timing deviations that occurred with separate AND circuits for each latch.
2Speed
If the latch circuits operate continuously to maintain readiness, then response time is reduced, but power consumption increases
Solution Approach 1:
The latch circuits are designed to operate periodically rather than continuously. They are enabled only during specific time windows when the control signal is active, which occurs periodically in sync with the AD conversion process. This periodic operation maintains readiness for conversions while consuming power only when needed, rather than continuously.
3Adaptability or versatility
If multiple control signals are generated with different timing to optimize latch operations, then operational flexibility is improved, but timing synchronization becomes difficult causing errors
Solution Approach 1:
The patent introduces an intermediary control signal that is generated by a single AND circuit and then distributed to multiple latch circuits. This intermediary signal acts as a mediator that ensures all latch circuits receive the same control timing information, maintaining synchronization while still allowing flexible control of the latch operations through the comparison output signal and its inverted delayed version.
Data Source
AI summary
An AD conversion circuit includes: a comparison unit that receives an analog signal and a reference signal, compares voltages of the signals, and outputs a first comparison signal; a signal generation unit that outputs a second comparison signal for switching a logic state, and outputs a third comparison signal that is a result of a logic operation on the first comparison signal and the second comparison signal; a control unit that outputs an enable signal; a clock generation unit that outputs first to nth clock signals having different phases; a latch unit that includes first to nth latch units, each of the first to nth latch units including an input terminal, a first control terminal, a second control terminal, and an output terminal, and latches a logic state of the one of the first to nth clock signals; and a count unit that performs a count operation.