Image Sensor ADC Linearity via Blocking Circuit Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
CMOS image sensors face challenges in achieving high-speed photography and high color sensitivity at low luminance, particularly due to limitations in the linearity of analog-to-digital converters, which affect image quality.
Innovation Solution
The image sensor incorporates a pixel array connected to column lines, with multiple analog-to-digital converters that compare pixel signals to a ramp signal, and a blocking circuit to isolate the influence of other converters, using NMOS and PMOS transistors and current sources to buffer and generate the ramp signal, enhancing linearity and image processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple analog-to-digital converters are used to process pixel signals from multiple column lines, then the processing speed and productivity are improved, but the linearity of the converters deteriorates due to mutual interference and operational influence between converters
Solution Approach 1:
The patent divides the pixel array into multiple banks, with each bank processed by a dedicated analog-to-digital converter. This segmentation isolates the processing of different pixel groups, preventing mutual interference between converters while maintaining high processing throughput through parallel operation of multiple converters.
Solution Approach 2:
The patent introduces a blocking circuit as an intermediary component between the pixel array and the analog-to-digital converters. This blocking circuit selectively controls the transmission of pixel signals to specific converters, preventing operational influence from one converter affecting another, thereby maintaining linearity while enabling parallel processing.
2Manufacturing precision
If the number of pixels is increased to at least ten million for high-resolution imaging, then the image quality is improved, but the complexity of the system increases and the operating speed requirements become more demanding
Solution Approach 1:
The patent organizes the ten million or more pixels into multiple banks, with each bank containing a manageable number of pixels. This segmentation reduces the complexity of signal routing and converter allocation while maintaining high-resolution imaging capability through the aggregated output of multiple converters.
Solution Approach 2:
The patent designs the blocking circuit and ramp signal generator to serve multiple analog-to-digital converters simultaneously. These components perform universal functions across all converters, reducing the need for dedicated components for each converter and thereby reducing overall system complexity despite the high pixel count.
3Speed
If the operating speed of the counter is increased to at least 1 GHz for high-speed photography, then the photography speed is improved, but the linearity of the analog-to-digital converter may deteriorate due to operational interference
Solution Approach 1:
The patent assigns different pixel banks to different analog-to-digital converters operating in parallel at high speeds. This segmentation ensures that the high-speed operation of one converter does not interfere with the linearity or operation of other converters, as each converter processes independent pixel data streams.
Solution Approach 2:
The blocking circuit acts as an intermediary that isolates the high-speed operation of each converter from affecting others. By controlling which pixel signals are routed to which converter, the blocking circuit prevents operational interference even at 1 GHz operating speeds, maintaining linearity across all converters.
Data Source
AI summary
An image sensor and an image processing system including the same are provided. The image sensor includes a pixel array including a plurality of pixels each connected to one of first through m-th column lines to output a pixel signal, where “m” is an integer of at least 2; analog-to-digital converters each configured to receive the pixel signal corresponding to one of the first through m-th column lines, to compare the pixel signal with a ramp signal, and to convert the pixel signal to a digital pixel signal; and a blocking circuit connected to an input terminal of at least one of the analog-to-digital converters to block an influence of an operation of others among the analog-to-digital converters.