Image Sensor ADC With Continuous CDS for Smaller Capacitors
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Solution Overview
Problem
Prior art analog to digital converters for image sensors face challenges in increasing resolution while minimizing the size of the image sensor package, as larger capacitors are required to reduce kT/C noise, leading to increased overall sensor size.
Innovation Solution
The proposed analog to digital converter employs a correlated double sample circuit with continuously connected sample capacitors and a time varying reference signal, allowing for the sampling of offset voltages and thermal noise, which reduces the need for large capacitors by mitigating sample and hold noise through continuous connection to a ramp generator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If capacitor size is increased to reduce kT/C noise, then measurement precision is improved, but area of stationary object increases
Solution Approach 1:
The patent applies preliminary action by sampling the kT/C noise during the reset period before the actual pixel signal is sampled. The CDS circuit captures the noise component on the capacitors during reset, then subtracts it from the pixel signal in the correlated double sampling process, thereby reducing noise without requiring larger capacitors.
Solution Approach 2:
The patent employs feedback through the correlated double sampling mechanism where the reset signal (containing kT/C noise) is fed back and subtracted from the pixel signal. This feedback loop allows the circuit to actively cancel noise components, achieving high measurement precision with smaller capacitor sizes.
2Measurement precision
If capacitor size is increased to reduce sample and hold noise, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by continuously connecting the sample capacitors to the ramp generator throughout both reset and read periods, rather than using switch-based isolation. This continuous connection simplifies the circuit architecture while enabling noise sampling during reset and correlated subtraction, achieving high precision without complex switching mechanisms.
Solution Approach 2:
The patent implements continuity of useful action by maintaining continuous connection between the sample capacitors and the ramp generator throughout the entire pixel readout period. This continuous connection allows the capacitors to continuously track the reference signal, enabling effective noise cancellation without requiring complex periodic switching or isolation mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the use of smaller sample capacitors, reducing the overall size of the image sensor while maintaining effective noise reduction, and allows for longer pixel on-time, enhancing resolution without increasing the sensor's physical dimensions.
Implementation Method 1
during correlated double sampling, kT/C noise or reset noise is cancelled by sampling the kT/C noise during reset before sampling the pixel signal onto the capacitors
Implementation Method 2
a correlated double sample circuit having first and second sample capacitors
Data Source
AI summary
An image sensor includes a pixel array, and a correlated double sample circuit coupled to one of the pixels in the pixel array. The correlated double sample circuit includes first and second inputs, and first and second sample capacitors respectively coupled to the first and second inputs. The first input is for receiving an analog signal from a pixel, and the second input is for receiving a time varying reference signal. The analog signal varies during a pixel readout period, and has a first level during a first reset period and a second-level during a second read period. A comparator circuit compares the time varying reference signal and the analog signal. The analog signal and the time varying reference signal are constantly read onto one of the first and second sample capacitors during both the first reset period and the second read period.