Image Sensor ADC Clock Gating to Limit Peak Current
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Solution Overview
Problem
CMOS image sensors experience peak current issues during multi-bit toggling, leading to deteriorated pixel data quality and system abnormalities, which existing techniques fail to adequately address.
Innovation Solution
An analog-digital converter with a count code generator, latch, operating circuit, and transfer controller, along with a comparator and counter, is used to manage pixel signals and reference signals, controlling the transfer of count codes based on clock signals to prevent peak current spikes and maintain data quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-bit toggling is performed during counting operation, then counting speed is improved, but peak current increases causing pixel data quality deterioration
Solution Approach 1:
The counting operation is divided into multiple sub-counting operations, where each sub-counter counts a portion of the total frames. This segmentation allows the system to achieve high-speed counting through parallel operation while limiting the current draw of each individual counter, thus avoiding peak current spikes that would otherwise occur with a single high-speed counter
Solution Approach 2:
The system uses periodic clock signals to control the counting operation in synchronized phases. By coordinating multiple sub-counters with periodic clock cycles and enabling them to operate in an interleaved manner, the system maintains high counting throughput while distributing current demand across different time periods, preventing simultaneous peak current draws
2Productivity
If counting operation is continuously performed, then productivity is improved, but power consumption increases
Solution Approach 1:
The counting operation is structured as a periodic process where sub-counters are enabled and disabled in alternating phases according to clock signals. This periodic activation allows continuous overall counting functionality while ensuring that not all counting circuits consume power simultaneously, thereby reducing total power consumption compared to continuous full-operation mode
Solution Approach 2:
The system discards the need for all sub-counters to operate continuously by utilizing only a subset of sub-counters at any given time. inactive sub-counters remain in a low-power state, and their counting capacity is recovered in subsequent phases, maintaining overall productivity while minimizing instantaneous power consumption
Data Source
AI summary
An analog-digital converter includes a count code generator to receive a code generation clock signal from a clock signal generator and to output a count code according to the code generation clock signal, a latch to latch the count code, an operating circuit to generate a count value of the count code and to output a digital signal based on the count value, and a transfer controller to transfer the count code from the latch to the operating circuit. The transfer controller determines whether to transfer the count code according to a logic level of a count enable clock signal generated from the clock signal generator.