Image Sensor ADC With Embedded CDS for Low-Noise Readout

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Solution Overview

Problem

Existing analogue to digital converters (ADCs) in image sensors face challenges in achieving high speed and high accuracy while maintaining low noise and high dynamic range, particularly due to noise contributions from pixels and readout elements.

Innovation Solution

The development of an analogue to digital converter with embedded analogue Correlated Double Sampling (CDS) that does not require a preceding CDS amplifier, allowing for internal CDS operations and oversampled sigma-delta techniques to reduce noise and enhance dynamic range.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If a CDS amplifier is used before the ADC, then noise from the pixel can be reduced through correlated double sampling, but the device complexity and number of components increase

Engineering Contradiction:
Improvenoise from pixelVSAvoidnumber of components
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The patent combines the CDS amplifier functionality directly into the ADC structure, eliminating the need for a separate CDS amplifier stage. The ADC is designed to perform correlated double sampling internally through its differential input configuration, where the first input receives the reset pixel value and the second input receives the signal pixel value, allowing noise cancellation to be integrated within the conversion process itself.

Inventive Principle:
Principle #5Merging (Combining)

2Speed

If multiple readout elements are used to increase processing speed, then the reading speed improves, but the area occupied by the readout element increases

Engineering Contradiction:
Improvereading speedVSAvoidarea occupied by readout element
Core Design Contradiction:
SpeedVSArea of stationary object

Solution Approach 1:

The ADC is designed with multi-functional capabilities to handle multiple pixel inputs and processing modes within a single structure. The differential input configuration allows the same ADC to process both reset and signal pixel values, and the architecture supports handling multiple pixel columns, enabling one readout element to perform the work of multiple simpler elements while occupying less area.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Productivity

If the ADC processes multiple pixel columns in parallel, then the reading speed increases, but the device complexity increases

Engineering Contradiction:
Improvereading speedVSAvoiddevice complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent divides the pixel matrix into multiple columns, each with its own readout node and ADC. This segmentation allows parallel processing of multiple columns while keeping each individual ADC relatively simple. The modular structure enables scalability where N columns can be processed by N independent but identical ADC units, distributing the complexity across multiple simple modules rather than requiring one complex centralized processor.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12289555B2Analogue to digital converter for image sensor readout
Publication Date: 2025.04.29 TELEDYNE INNOVACIONES MICROELECTRONICSAS SLU
  • US12289555B2 patent drawing
  • US12289555B2 patent drawing
  • US12289555B2 patent drawing

AI summary

An analogue to digital converter for converting the analogue output of a dual conversion gain pixel of an image sensor. The dual conversion gain pixel is operable to sequentially output a reset pixel value and a signal pixel value sequentially with both a first gain and a second gain different to the first gain. An image sensor comprising the analogue to digital converter, a system comprising the image sensor and a method are also described herein.