Image Sensor ADC Synchronization for Fast Low-Power Conversion
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Solution Overview
Problem
Existing analog-to-digital converters for image sensors face challenges in achieving high-speed conversion while minimizing power and area consumption, especially in image sensors with low pixel pitch and a large number of pixels, and they struggle to scale well with reduced supply voltages and increased transistor mismatch in smaller technology nodes.
Innovation Solution
The proposed analog-to-digital converter incorporates a synchronization circuit and a latch circuit to generate delayed write control signals, allowing the counter circuit to settle within half a clock period, enabling the use of asynchronous counter cells and optimizing power and area consumption. It also employs a shared counter circuit architecture and True Single Phase Clock (TSPC) cells to minimize clock and control signal load, and uses ripple counters for efficient bit generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional ADC architectures are used to achieve high-speed conversion, then conversion speed is improved, but power consumption and area consumption increase
Solution Approach 1:
The pixel array is divided into multiple pixel groups, each with its own dedicated counter circuit. This segmentation allows parallel processing of multiple pixel groups simultaneously, achieving high conversion speed while each individual counter circuit remains compact and power-efficient. The segmentation of the ADC functionality into group-parallel architecture enables speed improvement without proportionally increasing total power consumption.
Solution Approach 2:
The ADC employs a periodic ramp voltage that cycles through a range of voltage levels. This periodic action enables the counter circuit to reset and recount for each new conversion cycle, allowing high-speed repeated conversions. The ramp voltage periodically resets the counter, enabling continuous high-speed operation without requiring complex clearing mechanisms that would increase power consumption.
2Speed
If conventional ADC architectures are used to achieve high-speed conversion, then conversion speed is improved, but area consumption increases
Solution Approach 1:
The pixel array is divided into multiple pixel groups, each with its own dedicated counter circuit. This segmentation allows parallel processing of multiple pixel groups simultaneously, achieving high conversion speed while each individual counter circuit remains compact and power-efficient. The segmentation of the ADC functionality into group-parallel architecture enables speed improvement without proportionally increasing total power consumption.
Solution Approach 2:
Each counter circuit is designed to be universal and can process multiple pixel groups sequentially or in parallel depending on configuration. The counter circuit performs multiple functions: counting photons from different pixel groups, resetting periodically, and outputting digital signals. This multi-functionality reduces the need for dedicated separate circuits for each pixel group, thereby reducing total area consumption while maintaining high conversion speed through parallel processing capabilities.
3Area of stationary object
If smaller technology nodes are used to reduce device size, then area consumption is reduced, but transistor mismatch increases affecting conversion accuracy
Solution Approach 1:
The ADC circuit incorporates preliminary calibration and matching actions performed during manufacturing or initialization. The counter circuit and associated components are pre-characterized to account for transistor mismatch variations. This preliminary action compensates for the increased mismatch in smaller technology nodes, maintaining conversion accuracy despite the reduced device dimensions and smaller transistor geometries.
Solution Approach 2:
The ADC employs parameter changes in the ramp voltage characteristics and counter circuit operating conditions to compensate for transistor mismatch. By dynamically adjusting voltage levels, timing parameters, and counting thresholds based on measured mismatch characteristics, the system maintains high conversion accuracy. This parameter adaptation allows the use of smaller technology nodes for area reduction while correcting for the resulting increased transistor variability.
Data Source
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AI summary
An analog-to-digital converter for an image sensor comprises a counter circuit (110) to generate a respective counter bit (CNT<0>, CNT<1>, ..., CNT<N-1>) in response to a counter state of the counter circuit (110), and a storage circuit (130) for storing a respective storage state in response the respective counter bit (CNT<0>, CNT<1>, ..., CNT<N-1>). The converter further comprises a comparator circuit (150) for generating a level of a comparison signal (COMP), and a synchronization circuit (160) to generate a write control signal (WRITE) for controlling the storing of the respective storage state in the respective storage cell (140a, 140b, ..., 140n). The counter circuit (110) is configured to change the counter state, when a first edge (E1) of a cycle (CY) of the clock signal (CLK) is applied to the counter circuit (110), and to generate the write control signal (WRITE), when a second edge (E2) of the cycle (CY) of the clock signal (CLK) being subsequent to the first edge (E1) of the cycle (CY) of the clock signal (CLK) is applied to the synchronization circuit (160) .