Image Sensor A/D Converter Timing to Prevent DNL Deterioration
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Solution Overview
Problem
Integration type A/D converter circuits in image sensors experience deterioration of Differential Non-Linearity (DNL) and malfunction when speed is increased, leading to image quality issues such as distortion and horizontal streaks due to skew between lower and upper bit counter signals.
Innovation Solution
A semiconductor device with a lower counter circuit, lower bit latch circuit, upper counter circuit, and upper bit latch circuit, along with a comparison voltage generating circuit and decision circuit, is used to adjust and synchronize counter signals, preventing skew and maintaining accurate A/D conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the integration type A/D conversion circuit operates at higher speed to meet increasing frame rates and pixel counts, then productivity is improved, but DNL (Differential Non-Linearity) deteriorates and malfunctions occur due to skew between counter signals
Solution Approach 1:
The patent segments the counter circuit into multiple independent counter units (first counter unit, second counter unit, etc.), each handling different bit ranges of the counter signal. This segmentation allows each counter unit to operate independently with controlled signal propagation paths, reducing skew between different counter signals and preventing DNL deterioration even at high conversion speeds
Solution Approach 2:
The patent introduces a delay adjustment circuit as an intermediary element that receives counter signals from multiple counter units and adjusts their timing to synchronize them before combining. This intermediary component compensates for propagation delays and skew, ensuring accurate A/D conversion results at high speeds without DNL deterioration
2Productivity
If the A/D conversion speed is increased to handle higher frame rates, then productivity is improved, but signal skew causes malfunction and image quality degradation
Solution Approach 1:
The patent implements dynamic delay adjustment where the delay adjustment circuit adaptively compensates for propagation delays in counter signals based on their actual arrival times. This dynamic timing synchronization ensures that counter signals from different units are properly aligned even as operating conditions and speeds change, maintaining reliability at high frame rates
Solution Approach 2:
The patent applies preliminary delay adjustment to counter signals before they are combined in the A/D conversion process. By pre-synchronizing the timing of counter signals from multiple units in advance, the system prevents skew-related malfunctions before they occur, ensuring reliable operation at increased frame rates
Data Source
AI summary
The present invention provides a semiconductor device having an integration type A/D converter capable of speeding up. The semiconductor device includes a Johnson counter 18 for transmitting a lower bit counter signal JC<3:0>, a lower bit latch circuit 11 for outputting a lower bit latch result signal by a lower bit counter signal JC<3:0> and a lower bit latch signal 14, a determination circuit 12 for outputting an upper bit latch signal 15 by a lower bit latch signal 14, a binary gray converter circuit 20 for transmitting an upper bit counter signal GR<n:3>, and an upper bit latch circuit 13 for outputting an upper bit latch result signal by an upper bit counter signal GR<n:3> and an upper bit latch signal 15.