High Speed Rolling Image Sensor ADM Architecture
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Solution Overview
Problem
Conventional high-speed image sensors suffer from block noise and distortion at the boundaries of stacked chip implementations, which affect the accuracy of captured images and introduce ADC variations due to the separation of pixel signal lines.
Innovation Solution
A high-speed rolling CMOS image sensor using an Analog-to-Digital Converter and Memory (ADM) architecture, where pixel sub-arrays are partitioned into non-contiguous groups sharing a single ADC and memory unit tile, allowing parallel readout with reduced silicon area and minimizing boundary distortions by using multiple bit lines to connect each pixel column to readout circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If one column of pixels shares one readout circuit, then the frame rate increases, but the silicon area increases
Solution Approach 1:
The patent combines the ADC and memory into a single integrated unit tile structure, allowing multiple pixel columns to share this integrated unit. This merging reduces the total silicon area compared to having separate ADC and memory circuits for each column, while still enabling high frame rates through parallel processing of multiple columns.
Solution Approach 2:
The readout circuit is designed with multi-functional capabilities where a single readout circuit can service multiple pixel columns through time-multiplexed operation. The circuit performs both ADC conversion and memory storage functions within the same unit tile, reducing overall circuit count and silicon area while maintaining high frame rate capability.
2Productivity
If stacked chips are used to miniaturize image sensors, then the frame rate increases, but block noise and distortion occur at the boundaries of sub-portions
Solution Approach 1:
The pixel array is divided into multiple pixel groups, where each group is coupled to a dedicated readout circuit with its own ADC and memory unit tile. This segmentation allows independent processing of each group, eliminating the boundary distortion problems that occur in stacked chip architectures where sub-portions are processed separately. The segmentation maintains high frame rates through parallel processing of multiple groups simultaneously.
Data Source
AI summary
High speed rolling image sensor includes pixel array disposed in first semiconductor die, readout circuits disposed in second semiconductor die and conductors. Pixel array is partitioned into pixel sub-arrays (PSAs). Each of the PSAs includes a plurality of pixels. Pixel groups include pixels that are non-contiguous, non-overlapping and distinct. Each pixel group includes pixels from different PSAs. Each pixel group is coupled to a corresponding analog-to-digital converter and memory unit tiles (ADMs) respectively included in readout circuits. ADMs respectively include (i) analog-to-digital (ADC) circuits that convert the image data from pixel groups from analog to digital to obtain ADC outputs, and (ii) memory units to store ADC outputs. Conductors are coupling pixel array to ADMs. Conductors include number of conductors per column of pixel array. Number of conductors per column of pixel array may be equal to number of pixels in PSA arranged in same column. Other embodiments are described.