Stacked Image Sensor Air-Gap Bonding for Pixel Heat Isolation
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Solution Overview
Problem
In image sensors with stacked chip architecture, heat generated by the logic chip can cause increased dark current and Dark Image Non-Uniformity (DINU), particularly in hot operating environments, due to heat dissipation to neighboring pixel chips, leading to undesirable noise even in low light conditions.
Innovation Solution
The implementation of a stacked chip architecture with fluidly connected air gaps between the logic and pixel dies, utilizing raised oxide features to create thermal insulation, which limits heat transfer through both conduction and convection, thereby reducing thermal energy exchange between the logic and pixel chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If stacked chip architecture is used to consolidate size and shorten circuit connections, then device integration and compactness are improved, but heat transfer from logic chip to pixel chip increases causing dark current and DINU
Solution Approach 1:
The patent divides the interface between logic chip and pixel chip into multiple discrete bonding pads rather than a continuous bonding area. This segmentation creates air gaps between adjacent bonding pads, which act as thermal insulators to reduce heat transfer from the logic chip to the pixel chip while maintaining electrical connections through the bonded pads.
Solution Approach 2:
The patent introduces air gaps as an intermediary medium between the logic chip and pixel chip bonding surfaces. These air gaps serve as thermal insulators that block direct thermal conduction paths, thereby reducing heat transfer to the pixel chip while allowing electrical signals to pass through the bonded pads.
2Strength
If continuous oxide bonding is used between stacked chips, then bonding strength is improved, but thermal conduction increases causing dark current
Solution Approach 1:
The continuous oxide bonding layer is segmented into discrete bonding pads separated by air gaps. This segmentation maintains bonding strength at the pad locations while creating thermal barriers in the air gap regions, thereby reducing overall thermal conduction between chips.
Solution Approach 2:
The patent applies different properties to different regions: the bonding pads have high bonding strength and good thermal contact for electrical connections, while the air gap regions have low thermal conductivity for thermal insulation. This local differentiation of properties resolves the contradiction between bonding strength and thermal conduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution significantly reduces heat transfer between the logic and pixel chips, resulting in a 70% reduction in Dark Image Non-Uniformity, improving image sensor performance by minimizing dark current and noise, especially in high-temperature applications.
Implementation Method 1
utilizing raised oxide features to create thermal insulation, which limits heat transfer through both conduction and convection
Implementation Method 2
limits heat transfer through both conduction and convection
Implementation Method 3
limits heat transfer through both conduction and convection
Data Source
AI summary
Image sensors include a pixel die that is stacked on a logic die. The logic die includes at least one function logic element disposed on a bond side thereof, and a logic oxide array of raised logic oxide features also disposed on the bond side. The pixel die includes a pixel array disposed on a light receiving side thereof, and a pixel oxide array of raised pixel oxide features disposed on a bond side of the pixel die. A plurality of outer bonds is disposed between an outer region of the logic die and an outer region of the pixel die. A plurality of inner bonds is formed at an inner region of the image sensor between the pixel oxide array and the logic oxide array, the inner bonds being spaced apart by a plurality of fluidly connected air gaps that extend between the logic die and the pixel die.