Image Sensor Analog Dithering Clock Control for CFPN Reduction
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Solution Overview
Problem
Image sensing devices using the QDR scheme suffer from column fixed pattern noise (CFPN) due to column offsets in the analog-to-digital converters, which result in inconsistent digital signal generation across columns, leading to bright or dark overtones in image data.
Innovation Solution
The proposed image sensing device employs a clock signal control block generating variable logic combinations for clock control signals and a frequency division block controlling delay times to produce clock signals with different phases, allowing for analog-dithered digital signal processing that adjusts offset reflections for each unit row time, thereby reducing CFPN.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If QDR scheme is used to increase operation speed and reduce power consumption, then operation speed is improved and power consumption is reduced, but column fixed pattern noise occurs due to column offsets in ADCs
Solution Approach 1:
The patent applies dynamics by making the clock control signals variable rather than fixed. The clock signal control block generates clock control signals with variable logic combinations for each unit row time, and the frequency division block varies the delay times of clock signals based on control signals. This dynamic variation of clock timing parameters prevents consistent column offsets from manifesting as fixed pattern noise, while maintaining the high-speed QDR operation mode.
Solution Approach 2:
The patent changes the parameters of clock signals dynamically. Specifically, it varies the logic combinations of clock control signals and adjusts the delay times of clock signals passed to different ADCs. By changing these temporal parameters of the clock signals, the patent ensures that column offsets do not consistently affect the same columns, thereby reducing CFPN while maintaining high operation speed.
2Device complexity
If fixed clock signals are used in ADCs, then circuit design is simplified, but column offsets cause inconsistent digital signal generation across columns
Solution Approach 1:
The patent introduces a clock signal control block as an intermediary between the clock source and the ADCs. This intermediary block generates variable clock control signals that are then processed by the frequency division block to produce clock signals with varied timing characteristics for different ADCs. This intermediary mechanism allows for precise control of clock timing without significantly complicating the overall circuit design, thereby improving digital signal consistency while managing complexity.
3Stability of the object's composition
If clock signal delay times are fixed, then circuit operation is stable, but code offsets remain consistent causing CFPN
Solution Approach 1:
The patent applies dynamics by transforming fixed clock signal delay times into variable delay times. The frequency division block receives clock control signals with variable logic combinations and accordingly varies the delay times of clock signals sent to different ADCs. This dynamic adjustment ensures that code offsets do not remain consistent across columns, reducing CFPN while maintaining stable circuit operation through controlled variability.
Solution Approach 2:
The patent employs periodic variation of clock signal parameters. By varying the logic combinations of clock control signals periodically or systematically for each unit row time, the patent creates a patterned variation in clock timing that prevents consistent column offsets from producing fixed pattern noise, while maintaining overall circuit stability through regular, predictable operation cycles.
Data Source
AI summary
An image sensing device includes: a clock signal control block suitable for generating first and second clock control signals to have variable logic combinations for each unit row time; a frequency division block suitable for generating first and second clock signals having different phases based on a reference clock signal and controlling a first delay time reflected in the first clock signal and a second delay time reflected in the second clock signal for each unit row time based on the first and a second clock control signals; and a pixel signal processing block suitable for converting a pixel signal inputted for each unit row time into a digital signal based on the first and second clock signals.