Image Sensor Bias Control via Selective Transistor Coupling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Image sensors, such as CMOS sensors, face increased settling times and reduced pixel operation range due to loading associated with the sensor, which affects the correlated double sampling (CDS) time and frame rate.
Innovation Solution
The implementation of a bias control system using a first and second bias transistor to apply and remove biases to the pixel column, increasing the bias current to reduce settling time and enhance pixel operation by facilitating quicker settling and maintaining a saturation region of operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If loading associated with the sensor is increased, then pixel operation range is improved, but settling time increases
Solution Approach 1:
The patent implements dynamic bias control by selectively coupling bias transistors to the pixel column based on operational phase. During reset phase, additional bias transistors are activated to increase bias current and reduce settling time. During signal readout phase, the bias is reduced to maintain pixel operation range. This dynamic adjustment resolves the contradiction by adapting the bias level to the specific operational requirements of each phase.
Solution Approach 2:
The patent applies periodic bias adjustment synchronized with the pixel operation cycle. Bias transistors are selectively enabled during the reset phase and disabled during the signal readout phase, creating a periodic bias pattern that optimizes both settling time and pixel operation range at different times in the operational cycle.
2Loss of time
If bias current is increased to reduce settling time, then correlated double sampling time is reduced, but pixel operation may be degraded
Solution Approach 1:
The patent segments the bias control into multiple independent bias transistors that can be selectively activated. The first bias transistor provides baseline bias current for pixel operation, while the second bias transistor provides additional current specifically during reset phase. This segmentation allows independent optimization of bias current for different operational phases without compromising overall pixel performance.
Solution Approach 2:
The patent applies preliminary high bias current during the reset phase before signal readout begins. By increasing bias current in advance during reset, the pixel column settles faster, reducing the correlated double sampling time. The additional bias is removed before signal readout to maintain proper pixel operation range, thus achieving preliminary optimization without degradation.
Data Source
AI summary
One or more techniques or systems for bias control are provided herein. In some embodiments, the bias control relates to biasing of a column of one or more pixels for an image sensor. In some embodiments, an associated circuit includes a reset transistor, a source-follower transistor, a first transfer transistor, a first bias transistor, a second bias transistor, and a switch connected to the second bias transistor. In some embodiments, the first bias transistor and the second bias transistor bias a column of pixels at a first time. In some embodiments, the second bias transistor is turned off, thus removing a second bias at a second time. In this way, performance of the image sensor is improved, at least because the second bias transistor enables faster settling time when active, and a wide pixel operation range when switched off.